begin			if (clk_i'event and clk_i = '1') then				if (PIOsel = '0') then					store_pp_full <= PIOpp_full;				end if;			end if;		end process;		brty <= (ATA_DEV_ADR and w_acc) and (DMAtip or store_pp_full);	end block gen_bc_dec;	--	-- generate registers	--	register_block : block		signal sel_PIO_cmdport, sel_PIO_dport0, sel_PIO_dport1 : std_logic; -- PIO timing registers		signal sel_DMA_dev0, sel_DMA_dev1 : std_logic;                      -- DMA timing registers		signal sel_ctrl, sel_stat : std_logic;                              -- control / status register	begin		-- generate register select signals		sel_ctrl        <= CONsel and we_i and (ATA_ADR = ATA_CTRL_REG);		sel_stat        <= CONsel and we_i and (ATA_ADR = ATA_STAT_REG);		sel_PIO_cmdport <= CONsel and we_i and (ATA_ADR = ATA_PIO_CMD);		sel_PIO_dport0  <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP0);		sel_PIO_dport1  <= CONsel and we_i and (ATA_ADR = ATA_PIO_DP1);		sel_DMA_dev0    <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV0);		sel_DMA_dev1    <= CONsel and we_i and (ATA_ADR = ATA_DMA_DEV1);		-- reserved 0x1C-0x38 --		-- reserved 0x3C : DMA port --		-- generate control register		gen_ctrl_reg: process(clk_i, arst_i)		begin			if (arst_i = '0') then				CtrlReg(31 downto 1) <= (others => '0');				CtrlReg(0)           <= '1';                -- set reset bit			elsif (clk_i'event and clk_i = '1') then				if (rst_i = '1') then					CtrlReg(31 downto 1) <= (others => '0');					CtrlReg(0)           <= '1';                -- set reset bit				elsif (sel_ctrl = '1') then					CtrlReg <= dat_i;				end if;			end if;		end process gen_ctrl_reg;		-- assign bits		DMActrl_DMAen        <= CtrlReg(15);		DMActrl_dir          <= CtrlReg(13);		DMActrl_BeLeC1       <= CtrlReg(9);		DMActrl_BeLeC0       <= CtrlReg(8);		IDEctrl_IDEen        <= CtrlReg(7);		IDEctrl_FATR1        <= CtrlReg(6);		IDEctrl_FATR0        <= CtrlReg(5);		IDEctrl_ppen         <= CtrlReg(4);		PIO_dport1_IORDYen   <= CtrlReg(3);		PIO_dport0_IORDYen   <= CtrlReg(2);		PIO_cmdport_IORDYen  <= CtrlReg(1);		IDEctrl_rst          <= CtrlReg(0);		-- generate status register clearable bits		gen_stat_reg: block			signal dirq, int : std_logic;		begin			gen_irq: process(clk_i, arst_i)			begin				if (arst_i = '0') then					int  <= '0';					dirq <= '0';				elsif (clk_i'event and clk_i = '1') then					if (rst_i = '1') then						int  <= '0';						dirq <= '0';					else						int  <= (int or (irq and not dirq)) and not (sel_stat and not dat_i(0));						dirq <= irq;					end if;				end if;			end process gen_irq;			gen_stat: process(DMAtip, DMARxEmpty, DMATxFull, DMA_dmarq, PIOtip, int, PIOpp_full)			begin				StatReg(31 downto 0) <= (others => '0');                -- clear all bits (read unused bits as '0')				StatReg(31 downto 28) <= std_logic_vector(DeviceId);    -- set Device ID				StatReg(27 downto 24) <= std_logic_vector(RevisionNo);  -- set revision number				StatReg(15) <= DMAtip;				StatReg(10) <= DMARxEmpty;				StatReg(9)  <= DMATxFull;				StatReg(8)  <= DMA_dmarq;				StatReg(7)  <= PIOtip;				StatReg(6)  <= PIOpp_full;				StatReg(0)  <= int;			end process;		end block gen_stat_reg;		-- generate PIO compatible / command-port timing register		gen_PIO_cmdport_reg: process(clk_i, arst_i)		begin			if (arst_i = '0') then				PIO_cmdport_T1   <= conv_unsigned(PIO_mode0_T1, 8);				PIO_cmdport_T2   <= conv_unsigned(PIO_mode0_T2, 8);				PIO_cmdport_T4   <= conv_unsigned(PIO_mode0_T4, 8);				PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);			elsif (clk_i'event and clk_i = '1') then				if (rst_i = '1') then					PIO_cmdport_T1   <= conv_unsigned(PIO_mode0_T1, 8);					PIO_cmdport_T2   <= conv_unsigned(PIO_mode0_T2, 8);					PIO_cmdport_T4   <= conv_unsigned(PIO_mode0_T4, 8);					PIO_cmdport_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);				elsif (sel_PIO_cmdport = '1') then					PIO_cmdport_T1   <= unsigned(dat_i( 7 downto  0));					PIO_cmdport_T2   <= unsigned(dat_i(15 downto  8));					PIO_cmdport_T4   <= unsigned(dat_i(23 downto 16));					PIO_cmdport_Teoc <= unsigned(dat_i(31 downto 24));				end if;			end if;		end process gen_PIO_cmdport_reg;		-- generate PIO device0 timing register		gen_PIO_dport0_reg: process(clk_i, arst_i)		begin			if (arst_i = '0') then				PIO_dport0_T1   <= conv_unsigned(PIO_mode0_T1, 8);				PIO_dport0_T2   <= conv_unsigned(PIO_mode0_T2, 8);				PIO_dport0_T4   <= conv_unsigned(PIO_mode0_T4, 8);				PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);			elsif (clk_i'event and clk_i = '1') then				if (rst_i = '1') then					PIO_dport0_T1   <= conv_unsigned(PIO_mode0_T1, 8);					PIO_dport0_T2   <= conv_unsigned(PIO_mode0_T2, 8);					PIO_dport0_T4   <= conv_unsigned(PIO_mode0_T4, 8);					PIO_dport0_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);				elsif (sel_PIO_dport0 = '1') then					PIO_dport0_T1   <= unsigned(dat_i( 7 downto  0));					PIO_dport0_T2   <= unsigned(dat_i(15 downto  8));					PIO_dport0_T4   <= unsigned(dat_i(23 downto 16));					PIO_dport0_Teoc <= unsigned(dat_i(31 downto 24));				end if;			end if;		end process gen_PIO_dport0_reg;		-- generate PIO device1 timing register		gen_PIO_dport1_reg: process(clk_i, arst_i)		begin			if (arst_i = '0') then				PIO_dport1_T1   <= conv_unsigned(PIO_mode0_T1, 8);				PIO_dport1_T2   <= conv_unsigned(PIO_mode0_T2, 8);				PIO_dport1_T4   <= conv_unsigned(PIO_mode0_T4, 8);				PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);			elsif (clk_i'event and clk_i = '1') then				if (rst_i = '1') then					PIO_dport1_T1   <= conv_unsigned(PIO_mode0_T1, 8);					PIO_dport1_T2   <= conv_unsigned(PIO_mode0_T2, 8);					PIO_dport1_T4   <= conv_unsigned(PIO_mode0_T4, 8);					PIO_dport1_Teoc <= conv_unsigned(PIO_mode0_Teoc, 8);				elsif (sel_PIO_dport1 = '1') then					PIO_dport1_T1   <= unsigned(dat_i( 7 downto  0));					PIO_dport1_T2   <= unsigned(dat_i(15 downto  8));					PIO_dport1_T4   <= unsigned(dat_i(23 downto 16));					PIO_dport1_Teoc <= unsigned(dat_i(31 downto 24));				end if;			end if;		end process gen_PIO_dport1_reg;		-- generate DMA device0 timing register		gen_DMA_dev0_reg: process(clk_i, arst_i)		begin			if (arst_i = '0') then				DMA_dev0_Tm   <= conv_unsigned(DMA_mode0_Tm, 8);				DMA_dev0_Td   <= conv_unsigned(DMA_mode0_Td, 8);				DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);			elsif (clk_i'event and clk_i = '1') then				if (rst_i = '1') then					DMA_dev0_Tm   <= conv_unsigned(DMA_mode0_Tm, 8);					DMA_dev0_Td   <= conv_unsigned(DMA_mode0_Td, 8);					DMA_dev0_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);				elsif (sel_DMA_dev0 = '1') then					DMA_dev0_Tm   <= unsigned(dat_i( 7 downto  0));					DMA_dev0_Td   <= unsigned(dat_i(15 downto  8));					DMA_dev0_Teoc <= unsigned(dat_i(31 downto 24));				end if;			end if;		end process gen_DMA_dev0_reg;		-- generate DMA device1 timing register		gen_DMA_dev1_reg: process(clk_i, arst_i)		begin			if (arst_i = '0') then				DMA_dev1_Tm   <= conv_unsigned(DMA_mode0_Tm, 8);				DMA_dev1_Td   <= conv_unsigned(DMA_mode0_Td, 8);				DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);			elsif (clk_i'event and clk_i = '1') then				if (rst_i = '1') then					DMA_dev1_Tm   <= conv_unsigned(DMA_mode0_Tm, 8);					DMA_dev1_Td   <= conv_unsigned(DMA_mode0_Td, 8);					DMA_dev1_Teoc <= conv_unsigned(DMA_mode0_Teoc, 8);				elsif (sel_DMA_dev1 = '1') then					DMA_dev1_Tm   <= unsigned(dat_i( 7 downto  0));					DMA_dev1_Td   <= unsigned(dat_i(15 downto  8));					DMA_dev1_Teoc <= unsigned(dat_i(31 downto 24));				end if;			end if;		end process gen_DMA_dev1_reg;	end block register_block;	--	-- generate WISHBONE interconnect signals	--	gen_WB_sigs: block		signal Q : std_logic_vector(31 downto 0);	begin		-- generate acknowledge signal		ack_o <= PIOack or CONsel; -- or DMAack; -- since DMAack is derived from CONsel this is OK		-- generate error signal		err_o <= cyc_i and stb_i and berr;		-- generate retry signal		rty_o <= cyc_i and stb_i and brty;		-- assign interrupt signal		inta_o <= StatReg(0);			-- generate output multiplexor		with ATA_ADR select			Q <= CtrlReg when ATA_CTRL_REG, -- control register			     StatReg when ATA_STAT_REG, -- status register			     std_logic_vector(PIO_cmdport_Teoc & PIO_cmdport_T4 & PIO_cmdport_T2 & PIO_cmdport_T1) when ATA_PIO_CMD,  -- PIO compatible / cmd-port timing register			     std_logic_vector(PIO_dport0_Teoc & PIO_dport0_T4 & PIO_dport0_T2 & PIO_dport0_T1)     when ATA_PIO_DP0,  -- PIO fast timing register device0			     std_logic_vector(PIO_dport1_Teoc & PIO_dport1_T4 & PIO_dport1_T2 & PIO_dport1_T1)     when ATA_PIO_DP1,  -- PIO fast timing register device1			     std_logic_vector(DMA_dev0_Teoc & x"00" & DMA_dev0_Td & DMA_dev0_Tm)                   when ATA_DMA_DEV0, -- DMA timing register device0			     std_logic_vector(DMA_dev1_Teoc & x"00" & DMA_dev1_Td & DMA_dev1_Tm)                   when ATA_DMA_DEV1, -- DMA timing register device1			     DMAq    when ATA_DMA_PORT, -- DMA port, DMA receive register		       (others => '0') when others;		dat_o <= (x"0000" & PIOq) when (ATA_DEV_ADR = '1') else Q;	end block gen_WB_sigs;end architecture structural;