PIO_cmdport_T4,		PIO_cmdport_Teoc    : buffer unsigned(7 downto 0);		PIO_cmdport_IORDYen : out std_logic;		-- data-port0 timing registers		PIO_dport0_T1,		PIO_dport0_T2,		PIO_dport0_T4,		PIO_dport0_Teoc    : buffer unsigned(7 downto 0);		PIO_dport0_IORDYen : out std_logic;		-- data-port1 timing registers		PIO_dport1_T1,		PIO_dport1_T2,		PIO_dport1_T4,		PIO_dport1_Teoc    : buffer unsigned(7 downto 0);		PIO_dport1_IORDYen : out std_logic;		-- DMA device0 timing registers		DMA_dev0_Tm,		DMA_dev0_Td,		DMA_dev0_Teoc    : buffer unsigned(7 downto 0);		-- DMA device1 timing registers		DMA_dev1_Tm,		DMA_dev1_Td,		DMA_dev1_Teoc    : buffer unsigned(7 downto 0)	);	end component atahost_wb_slave;	component atahost_controller is	generic(		TWIDTH : natural := 8;                        -- counter width		-- PIO mode 0 settings (@100MHz clock)		PIO_mode0_T1 : natural := 6;                  -- 70ns		PIO_mode0_T2 : natural := 28;                 -- 290ns		PIO_mode0_T4 : natural := 2;                  -- 30ns		PIO_mode0_Teoc : natural := 23                -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240	);	port(		clk : in std_logic;                           -- master clock in		nReset : in std_logic := '1';                 -- asynchronous active low reset		rst : in std_logic := '0';                    -- synchronous active high reset				irq : out std_logic;                          -- interrupt request signal		-- control / registers		IDEctrl_rst,		IDEctrl_IDEen : in std_logic;		-- PIO registers		PIO_cmdport_T1,		PIO_cmdport_T2,		PIO_cmdport_T4,		PIO_cmdport_Teoc : in unsigned(7 downto 0);   -- PIO command timing		PIO_cmdport_IORDYen : in std_logic;		PIOreq : in std_logic;                        -- PIO transfer request		PIOack : buffer std_logic;                    -- PIO transfer ended		PIOa   : in unsigned(3 downto 0);             -- PIO address		PIOd   : in std_logic_vector(15 downto 0);    -- PIO data in		PIOq   : out std_logic_vector(15 downto 0);   -- PIO data out		PIOwe  : in std_logic;                        -- PIO direction bit '1'=write, '0'=read		-- ATA signals		RESETn : out std_logic;		DDi  	 : in  std_logic_vector(15 downto 0);		DDo    : out std_logic_vector(15 downto 0);		DDoe   : out std_logic;		DA     : out unsigned(2 downto 0);		CS0n   : out std_logic;		CS1n   : out std_logic;		DIORn	: out std_logic;		DIOWn	: out std_logic;		IORDY	: in  std_logic;		INTRQ	: in  std_logic	);	end component atahost_controller;	-- asynchronous reset signal	signal arst_signal : std_logic;	-- primary address decoder	signal PIOsel  : std_logic;  -- controller select, IDE devices select		-- registers	signal IDEctrl_IDEen, IDEctrl_rst: std_logic;	signal PIO_cmdport_T1, PIO_cmdport_T2, PIO_cmdport_T4, PIO_cmdport_Teoc : unsigned(7 downto 0);	signal PIO_cmdport_IORDYen : std_logic;	signal PIOack : std_logic;	signal PIOq : std_logic_vector(15 downto 0);	signal irq : std_logic; -- ATA bus IRQ signalbegin	-- generate asynchronous reset level	arst_signal <= arst_i xor ARST_LVL;	--	-- hookup wishbone slave	--	u0: atahost_wb_slave 		generic map(			DeviceID   => DeviceID,			RevisionNo => RevisionNo,			-- PIO mode 0 settings			PIO_mode0_T1 => PIO_mode0_T1,			PIO_mode0_T2 => PIO_mode0_T2,			PIO_mode0_T4 => PIO_mode0_T4,			PIO_mode0_Teoc => PIO_mode0_Teoc,			-- Multiword DMA mode 0 settings			-- OCIDEC-1 does not support DMA, set registers to zero			DMA_mode0_Tm   => 0,			DMA_mode0_Td   => 0,			DMA_mode0_Teoc => 0		)		port map(			-- WISHBONE SYSCON signals			clk_i => wb_clk_i,			arst_i => arst_signal,			rst_i  => wb_rst_i,			-- WISHBONE SLAVE signals			cyc_i => wb_cyc_i,			stb_i => wb_stb_i,			ack_o => wb_ack_o,			err_o => wb_err_o,			adr_i => wb_adr_i,			dat_i => wb_dat_i,			dat_o => wb_dat_o,			sel_i => wb_sel_i,			we_i  => wb_we_i,			inta_o => wb_inta_o,			-- PIO control input			--	PIOtip is only asserted during a PIO transfer (No shit! ;)			--	Since it is impossible to read the status register and access the PIO registers at the same time			--	this bit is useless (besides using-up resources)			PIOtip     => '0',			PIOack     => PIOack,			PIOq       => PIOq,			PIOsel     => PIOsel,			PIOpp_full => '0', -- OCIDEC-1 does not support PIO-write PingPong, negate signal			irq        => irq,			-- DMA control inputs (negate all of them)			DMAtip     => '0',			DMAack     => '0',			DMARxEmpty => '0',			DMATxFull  => '0',			DMA_dmarq  => '0',			DMAq       => x"00000000",			-- outputs			-- control register outputs			IDEctrl_rst   => IDEctrl_rst,			IDEctrl_IDEen => IDEctrl_IDEen,			-- CMD port timing registers			PIO_cmdport_T1 => PIO_cmdport_T1,			PIO_cmdport_T2 => PIO_cmdport_T2,			PIO_cmdport_T4 => PIO_cmdport_T4,			PIO_cmdport_Teoc => PIO_cmdport_Teoc,			PIO_cmdport_IORDYen => PIO_cmdport_IORDYen		);	--	-- hookup controller section	--	u1: atahost_controller		generic map(			TWIDTH         => TWIDTH,			PIO_mode0_T1   => PIO_mode0_T1,			PIO_mode0_T2   => PIO_mode0_T2,			PIO_mode0_T4   => PIO_mode0_T4,			PIO_mode0_Teoc => PIO_mode0_Teoc		)		port map(			clk    => wb_clk_i,			nReset => arst_signal,			rst    => wb_rst_i,			irq    => irq,			IDEctrl_rst         => IDEctrl_rst,			IDEctrl_IDEen       => IDEctrl_IDEen,			PIO_cmdport_T1      => PIO_cmdport_T1,			PIO_cmdport_T2      => PIO_cmdport_T2,			PIO_cmdport_T4      => PIO_cmdport_T4,			PIO_cmdport_Teoc    => PIO_cmdport_Teoc,			PIO_cmdport_IORDYen => PIO_cmdport_IORDYen, 			PIOreq => PIOsel,			PIOack => PIOack,			PIOa   => wb_adr_i(5 downto 2),			PIOd   => wb_dat_i(15 downto 0),			PIOq   => PIOq,			PIOwe  => wb_we_i,			RESETn => resetn_pad_o,			DDi    => dd_pad_i,			DDo    => dd_pad_o,			DDoe   => dd_padoe_o,			DA     => da_pad_o,			CS0n   => cs0n_pad_o,			CS1n   => cs1n_pad_o,			DIORn  => diorn_pad_o,			DIOWn  => diown_pad_o,			IORDY  => iordy_pad_i,			INTRQ  => intrq_pad_i		);end architecture structural;