-----------------------------Revision: 1.0Date: march 22nd, 2001Author: Richard Herveille- initial release----------------------------------------------------------Revision: 1.0aDate: april 12th, 2001Author: Richard Herveille- removed records.vhd- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools- fixed a minor bug where core didn't respond to IDEen bit.----------------------------------------------------------Revision: 1.1Date: June 18th, 2001Author: Richard Herveille- Changed PIOack generation. Avoid asserting PIOack continuosly when IDEen = '0'- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2)----------------------------------------------------------Revision: 1.1aDate: June 19th, 2001Author: Richard Herveille- Missed a reference to ADR_I(4). Simplified DAT_O output multiplexor.----------------------------------------------------------Revision: 1.2Date: June 26th, 2001Author: Richard Herveille- Changed dPIOreq generation (controller.vhd). Wishbone burst accesses to ata device were not handled correctly- Change PIOack from "out" to "buffer" (controller.vhd + ata.vhd)----------------------------------------------------------Revision: 1.3Date: July 11th, 2001Author: Richard Herveille- renamed 'ata.vhd' to 'atahost.vhd'- Changed PIOreq & PIOack generation (controller.vhd); made them synchronous- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).----------------------------------------------------------Revision: 1.4Date: Februar 17th, 2002Author: Richard Herveille- renamed 'atahost.vhd' to 'atahost_top.vhd'- renamed 'controller.vhd' to 'atahost_controller.vhd'- renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd'- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'- changed resD input to generic RESD in ud_cnt.vhd- changed ID input to generic ID in ro_cnt.vhd- changed core to reflect changes in ro_cnt.vhd- removed references to 'count' library- changed IO names- added disclaimer- added CVS log- moved registers and wishbone signals into 'atahost_wb_slave.vhd'- core is now equivalent to verilog version----------------------------------------------------------Revision: 1.5Date: May 19th, 2002.Author: Richard Herveille- Fixed a potential bug that forced the core into an unknown state  when an asynchronous reset was given without a running clock-----------------------------