?? standard.pin
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- Bank 9: 3.3V
-- Bank 10: 3.3V
-- Bank 11: 3.3V
-- Bank 12: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
---------------------------------------------------------------------------------
Quartus II Version 5.0 Build 146 04/13/2005 SJ Full Version
CHIP "standard" ASSIGNED TO AN: EP2S60F672C5ES
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A2 : gnd : : : :
cf_data[9] : A3 : bidir : LVTTL : : 4 : Y
VCCIO4 : A4 : power : : 3.3V : 4 :
cf_data[2] : A5 : bidir : LVTTL : : 4 : Y
cf_data[14] : A6 : bidir : LVTTL : : 4 : Y
cf_iowr_n : A7 : output : LVTTL : : 4 : Y
RESERVED_INPUT : A8 : : : : 4 :
cf_cs_n[0] : A9 : output : LVTTL : : 4 : Y
cf_addr[9] : A10 : output : LVTTL : : 4 : Y
VCCIO4 : A11 : power : : 3.3V : 4 :
RESERVED_INPUT : A12 : : : : 9 :
GND : A13 : gnd : : : :
GND : A14 : gnd : : : :
RESERVED_INPUT : A15 : : : : 3 :
VCCIO3 : A16 : power : : 3.3V : 3 :
RESERVED_INPUT : A17 : : : : 3 :
RESERVED_INPUT : A18 : : : : 3 :
RESERVED_INPUT : A19 : : : : 3 :
RESERVED_INPUT : A20 : : : : 3 :
RESERVED_INPUT : A21 : : : : 3 :
RESERVED_INPUT : A22 : : : : 3 :
VCCIO3 : A23 : power : : 3.3V : 3 :
RESERVED_INPUT : A24 : : : : 3 :
GND : A25 : gnd : : : :
ext_ram_bus_address[10] : AA1 : output : LVTTL : : 6 : Y
ext_ram_bus_address[11] : AA2 : output : LVTTL : : 6 : Y
ext_ram_bus_address[18] : AA3 : output : LVTTL : : 6 : Y
ext_ram_bus_address[19] : AA4 : output : LVTTL : : 6 : Y
ext_ram_bus_data[30] : AA5 : bidir : LVTTL : : 6 : Y
ext_ram_bus_data[31] : AA6 : bidir : LVTTL : : 6 : Y
GND : AA7 : gnd : : : :
zs_dq_to_and_from_the_sdram[30] : AA8 : bidir : LVTTL : : 7 : Y
VREFB7 : AA9 : power : : : 7 :
zs_addr_from_the_sdram[10] : AA10 : output : LVTTL : : 7 : Y
RESERVED_INPUT : AA11 : : : : 7 :
RESERVED_INPUT : AA12 : : : : 7 :
GND : AA13 : gnd : : : :
RESERVED_INPUT : AA14 : : : : 8 :
PLD_CLEAR_N : AA15 : input : LVTTL : : 8 : Y
zs_dq_to_and_from_the_sdram[2] : AA16 : bidir : LVTTL : : 8 : Y
zs_dq_to_and_from_the_sdram[7] : AA17 : bidir : LVTTL : : 8 : Y
VREFB8 : AA18 : power : : : 8 :
RESERVED_INPUT : AA19 : : : : 8 :
nCONFIG : AA20 : : : : 8 :
RESERVED_INPUT : AA21 : : : : 1 :
RESERVED_INPUT : AA22 : : : : 1 :
RESERVED_INPUT : AA23 : : : : 1 :
RESERVED_INPUT : AA24 : : : : 1 :
RESERVED_INPUT : AA25 : : : : 1 :
RESERVED_INPUT : AA26 : : : : 1 :
ext_ram_bus_address[12] : AB1 : output : LVTTL : : 6 : Y
ext_ram_bus_address[13] : AB2 : output : LVTTL : : 6 : Y
ext_ram_bus_address[20] : AB3 : output : LVTTL : : 6 : Y
ext_ram_bus_address[21] : AB4 : output : LVTTL : : 6 : Y
nCEO : AB5 : : : : 7 :
PLL_ENA : AB6 : : : : 7 :
zs_dq_to_and_from_the_sdram[28] : AB7 : bidir : LVTTL : : 7 : Y
RESERVED_INPUT : AB8 : : : : 7 :
read_n_to_the_ext_flash : AB9 : output : LVTTL : : 7 : Y
zs_addr_from_the_sdram[5] : AB10 : output : LVTTL : : 7 : Y
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