?? urat.tan.qmsg

?? VHDL語言編寫的全功能串口模塊（包含DTR
?? QMSG
?? 第 1 頁 / 共 3 頁
字號:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkbaud8x " "Info: Detected ripple clock \"clkbaud8x\" as buffer" {  } { { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 100 -1 0 } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clkbaud8x" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register state_tras\[1\] register txd_buf\[0\] 211.33 MHz 4.732 ns Internal " "Info: Clock \"clk\" has Internal fmax of 211.33 MHz between source register \"state_tras\[1\]\" and destination register \"txd_buf\[0\]\" (period= 4.732 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.471 ns + Longest register register " "Info: + Longest register to register delay is 4.471 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state_tras\[1\] 1 REG LC_X20_Y11_N7 21 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y11_N7; Fanout = 21; REG Node = 'state_tras\[1\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { state_tras[1] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.590 ns) 1.910 ns trasstart~688 2 COMB LC_X20_Y12_N3 3 " "Info: 2: + IC(1.320 ns) + CELL(0.590 ns) = 1.910 ns; Loc. = LC_X20_Y12_N3; Fanout = 3; COMB Node = 'trasstart~688'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.910 ns" { state_tras[1] trasstart~688 } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.438 ns) + CELL(0.442 ns) 2.790 ns txd_buf\[0\]~1264 3 COMB LC_X20_Y12_N4 5 " "Info: 3: + IC(0.438 ns) + CELL(0.442 ns) = 2.790 ns; Loc. = LC_X20_Y12_N4; Fanout = 5; COMB Node = 'txd_buf\[0\]~1264'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.880 ns" { trasstart~688 txd_buf[0]~1264 } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.814 ns) + CELL(0.867 ns) 4.471 ns txd_buf\[0\] 4 REG LC_X21_Y12_N2 3 " "Info: 4: + IC(0.814 ns) + CELL(0.867 ns) = 4.471 ns; Loc. = LC_X21_Y12_N2; Fanout = 3; REG Node = 'txd_buf\[0\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.681 ns" { txd_buf[0]~1264 txd_buf[0] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.899 ns ( 42.47 % ) " "Info: Total cell delay = 1.899 ns ( 42.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.572 ns ( 57.53 % ) " "Info: Total interconnect delay = 2.572 ns ( 57.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.471 ns" { state_tras[1] trasstart~688 txd_buf[0]~1264 txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "4.471 ns" { state_tras[1] trasstart~688 txd_buf[0]~1264 txd_buf[0] } { 0.000ns 1.320ns 0.438ns 0.814ns } { 0.000ns 0.590ns 0.442ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.247 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_C7 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C7; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.198 ns) + CELL(0.935 ns) 7.608 ns clkbaud8x 2 REG LC_X11_Y8_N2 22 " "Info: 2: + IC(5.198 ns) + CELL(0.935 ns) = 7.608 ns; Loc. = LC_X11_Y8_N2; Fanout = 22; REG Node = 'clkbaud8x'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.133 ns" { clk clkbaud8x } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.928 ns) + CELL(0.711 ns) 12.247 ns txd_buf\[0\] 3 REG LC_X21_Y12_N2 3 " "Info: 3: + IC(3.928 ns) + CELL(0.711 ns) = 12.247 ns; Loc. = LC_X21_Y12_N2; Fanout = 3; REG Node = 'txd_buf\[0\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.639 ns" { clkbaud8x txd_buf[0] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 25.48 % ) " "Info: Total cell delay = 3.121 ns ( 25.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.126 ns ( 74.52 % ) " "Info: Total interconnect delay = 9.126 ns ( 74.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_buf[0] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.247 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_C7 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C7; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.198 ns) + CELL(0.935 ns) 7.608 ns clkbaud8x 2 REG LC_X11_Y8_N2 22 " "Info: 2: + IC(5.198 ns) + CELL(0.935 ns) = 7.608 ns; Loc. = LC_X11_Y8_N2; Fanout = 22; REG Node = 'clkbaud8x'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.133 ns" { clk clkbaud8x } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.928 ns) + CELL(0.711 ns) 12.247 ns state_tras\[1\] 3 REG LC_X20_Y11_N7 21 " "Info: 3: + IC(3.928 ns) + CELL(0.711 ns) = 12.247 ns; Loc. = LC_X20_Y11_N7; Fanout = 21; REG Node = 'state_tras\[1\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.639 ns" { clkbaud8x state_tras[1] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 25.48 % ) " "Info: Total cell delay = 3.121 ns ( 25.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.126 ns ( 74.52 % ) " "Info: Total interconnect delay = 9.126 ns ( 74.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x state_tras[1] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x state_tras[1] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_buf[0] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x state_tras[1] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x state_tras[1] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.471 ns" { state_tras[1] trasstart~688 txd_buf[0]~1264 txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "4.471 ns" { state_tras[1] trasstart~688 txd_buf[0]~1264 txd_buf[0] } { 0.000ns 1.320ns 0.438ns 0.814ns } { 0.000ns 0.590ns 0.442ns 0.867ns } } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_buf[0] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x state_tras[1] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x state_tras[1] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "txd_buf\[0\] key_input clk -2.372 ns register " "Info: tsu for register \"txd_buf\[0\]\" (data pin = \"key_input\", clock pin = \"clk\") is -2.372 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.838 ns + Longest pin register " "Info: + Longest pin to register delay is 9.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key_input 1 PIN PIN_G15 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_G15; Fanout = 18; PIN Node = 'key_input'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_input } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.098 ns) + CELL(0.590 ns) 8.157 ns txd_buf\[0\]~1264 2 COMB LC_X20_Y12_N4 5 " "Info: 2: + IC(6.098 ns) + CELL(0.590 ns) = 8.157 ns; Loc. = LC_X20_Y12_N4; Fanout = 5; COMB Node = 'txd_buf\[0\]~1264'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.688 ns" { key_input txd_buf[0]~1264 } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.814 ns) + CELL(0.867 ns) 9.838 ns txd_buf\[0\] 3 REG LC_X21_Y12_N2 3 " "Info: 3: + IC(0.814 ns) + CELL(0.867 ns) = 9.838 ns; Loc. = LC_X21_Y12_N2; Fanout = 3; REG Node = 'txd_buf\[0\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.681 ns" { txd_buf[0]~1264 txd_buf[0] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.926 ns ( 29.74 % ) " "Info: Total cell delay = 2.926 ns ( 29.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.912 ns ( 70.26 % ) " "Info: Total interconnect delay = 6.912 ns ( 70.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.838 ns" { key_input txd_buf[0]~1264 txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "9.838 ns" { key_input key_input~out0 txd_buf[0]~1264 txd_buf[0] } { 0.000ns 0.000ns 6.098ns 0.814ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.247 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 12.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_C7 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C7; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.198 ns) + CELL(0.935 ns) 7.608 ns clkbaud8x 2 REG LC_X11_Y8_N2 22 " "Info: 2: + IC(5.198 ns) + CELL(0.935 ns) = 7.608 ns; Loc. = LC_X11_Y8_N2; Fanout = 22; REG Node = 'clkbaud8x'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.133 ns" { clk clkbaud8x } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.928 ns) + CELL(0.711 ns) 12.247 ns txd_buf\[0\] 3 REG LC_X21_Y12_N2 3 " "Info: 3: + IC(3.928 ns) + CELL(0.711 ns) = 12.247 ns; Loc. = LC_X21_Y12_N2; Fanout = 3; REG Node = 'txd_buf\[0\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.639 ns" { clkbaud8x txd_buf[0] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 25.48 % ) " "Info: Total cell delay = 3.121 ns ( 25.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.126 ns ( 74.52 % ) " "Info: Total interconnect delay = 9.126 ns ( 74.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_buf[0] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.838 ns" { key_input txd_buf[0]~1264 txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "9.838 ns" { key_input key_input~out0 txd_buf[0]~1264 txd_buf[0] } { 0.000ns 0.000ns 6.098ns 0.814ns } { 0.000ns 1.469ns 0.590ns 0.867ns } } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_buf[0] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_buf[0] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk out_data\[7\] txd_buf\[7\] 17.994 ns register " "Info: tco from clock \"clk\" to destination pin \"out_data\[7\]\" through register \"txd_buf\[7\]\" is 17.994 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.247 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_C7 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C7; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.198 ns) + CELL(0.935 ns) 7.608 ns clkbaud8x 2 REG LC_X11_Y8_N2 22 " "Info: 2: + IC(5.198 ns) + CELL(0.935 ns) = 7.608 ns; Loc. = LC_X11_Y8_N2; Fanout = 22; REG Node = 'clkbaud8x'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.133 ns" { clk clkbaud8x } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.928 ns) + CELL(0.711 ns) 12.247 ns txd_buf\[7\] 3 REG LC_X19_Y12_N2 3 " "Info: 3: + IC(3.928 ns) + CELL(0.711 ns) = 12.247 ns; Loc. = LC_X19_Y12_N2; Fanout = 3; REG Node = 'txd_buf\[7\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.639 ns" { clkbaud8x txd_buf[7] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 25.48 % ) " "Info: Total cell delay = 3.121 ns ( 25.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.126 ns ( 74.52 % ) " "Info: Total interconnect delay = 9.126 ns ( 74.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_buf[7] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_buf[7] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.523 ns + Longest register pin " "Info: + Longest register to pin delay is 5.523 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns txd_buf\[7\] 1 REG LC_X19_Y12_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y12_N2; Fanout = 3; REG Node = 'txd_buf\[7\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { txd_buf[7] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.415 ns) + CELL(2.108 ns) 5.523 ns out_data\[7\] 2 PIN PIN_U14 0 " "Info: 2: + IC(3.415 ns) + CELL(2.108 ns) = 5.523 ns; Loc. = PIN_U14; Fanout = 0; PIN Node = 'out_data\[7\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.523 ns" { txd_buf[7] out_data[7] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 38.17 % ) " "Info: Total cell delay = 2.108 ns ( 38.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.415 ns ( 61.83 % ) " "Info: Total interconnect delay = 3.415 ns ( 61.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.523 ns" { txd_buf[7] out_data[7] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "5.523 ns" { txd_buf[7] out_data[7] } { 0.000ns 3.415ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_buf[7] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_buf[7] } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.523 ns" { txd_buf[7] out_data[7] } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "5.523 ns" { txd_buf[7] out_data[7] } { 0.000ns 3.415ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
?? 文件大小 219 K
?? 上傳用戶 yuyx2003
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關標簽

#VHDL #DTR #語言 #編寫
?? 快捷鍵說明

復制代碼 Ctrl + C
搜索代碼 Ctrl + F
全屏模式 F11
切換主題 Ctrl + Shift + D
顯示快捷鍵 ?
增大字號 Ctrl + =
減小字號 Ctrl + -
亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频

?? urat.tan.qmsg

?? 快捷鍵說明
