?? urat.pin
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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
---------------------------------------------------------------------------------
Quartus II Version 6.0 Build 178 04/27/2006 SJ Web Edition
CHIP "urat" ASSIGNED TO AN: EP1C4F324C8
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A1 : gnd : : : :
VCCINT : A2 : power : : 1.5V : :
GND : A3 : gnd : : : :
RESERVED_INPUT : A4 : : : : 2 :
VCCIO2 : A5 : power : : 3.3V : 2 :
RESERVED_INPUT : A6 : : : : 2 :
RESERVED_INPUT : A7 : : : : 2 :
RESERVED_INPUT : A8 : : : : 2 :
RESERVED_INPUT : A9 : : : : 2 :
RESERVED_INPUT : A10 : : : : 2 :
RESERVED_INPUT : A11 : : : : 2 :
RESERVED_INPUT : A12 : : : : 2 :
RESERVED_INPUT : A13 : : : : 2 :
VCCIO2 : A14 : power : : 3.3V : 2 :
RESERVED_INPUT : A15 : : : : 2 :
GND : A16 : gnd : : : :
VCCINT : A17 : power : : 1.5V : :
GND : A18 : gnd : : : :
VCCINT : B1 : power : : 1.5V : :
GND : B2 : gnd : : : :
RESERVED_INPUT : B3 : : : : 2 :
RESERVED_INPUT : B4 : : : : 2 :
RESERVED_INPUT : B5 : : : : 2 :
RESERVED_INPUT : B6 : : : : 2 :
RESERVED_INPUT : B7 : : : : 2 :
RESERVED_INPUT : B8 : : : : 2 :
RESERVED_INPUT : B9 : : : : 2 :
RESERVED_INPUT : B10 : : : : 2 :
RESERVED_INPUT : B11 : : : : 2 :
RESERVED_INPUT : B12 : : : : 2 :
RESERVED_INPUT : B13 : : : : 2 :
RESERVED_INPUT : B14 : : : : 2 :
RESERVED_INPUT : B15 : : : : 2 :
RESERVED_INPUT : B16 : : : : 2 :
GND : B17 : gnd : : : :
VCCINT : B18 : power : : 1.5V : :
GND : C1 : gnd : : : :
RESERVED_INPUT : C2 : : : : 1 :
~LVDS31p/INIT_DONE~ / RESERVED : C3 : output : LVTTL : : 1 : N
RESERVED_INPUT : C4 : : : : 2 :
RESERVED_INPUT : C5 : : : : 2 :
RESERVED_INPUT : C6 : : : : 2 :
clk : C7 : input : LVTTL : : 2 : Y
RESERVED_INPUT : C8 : : : : 2 :
RESERVED_INPUT : C9 : : : : 2 :
RESERVED_INPUT : C10 : : : : 2 :
RESERVED_INPUT : C11 : : : : 2 :
RESERVED_INPUT : C12 : : : : 2 :
RESERVED_INPUT : C13 : : : : 2 :
RESERVED_INPUT : C14 : : : : 2 :
RESERVED_INPUT : C15 : : : : 2 :
RESERVED_INPUT : C16 : : : : 2 :
RESERVED_INPUT : C17 : : : : 3 :
GND : C18 : gnd : : : :
RESERVED_INPUT : D1 : : : : 1 :
RESERVED_INPUT : D2 : : : : 1 :
RESERVED_INPUT : D3 : : : : 1 :
RESERVED_INPUT : D4 : : : : 1 :
RESERVED_INPUT : D5 : : : : 2 :
RESERVED_INPUT : D6 : : : : 2 :
RESERVED_INPUT : D7 : : : : 2 :
RESERVED_INPUT : D8 : : : : 2 :
RESERVED_INPUT : D9 : : : : 2 :
RESERVED_INPUT : D10 : : : : 2 :
RESERVED_INPUT : D11 : : : : 2 :
RESERVED_INPUT : D12 : : : : 2 :
RESERVED_INPUT : D13 : : : : 2 :
RESERVED_INPUT : D14 : : : : 2 :
RESERVED_INPUT : D15 : : : : 3 :
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