module w4(clk,dx,dy);
input clk;
output[7:0] dx,dy;

reg d;
reg[7:0] ds,dx,dy;
reg[9:0] st;
reg[15:0] d_zf;

wire[7:0] dx_=st[3:0];
wire[7:0] dy_=st[7:4];

always @(negedge clk)
begin
  if(d) 
    if(ds!=0) ds=ds-1;
    else begin ds=100;st=st+1;end
  else begin ds=100;st=st+1;end
end

always @(negedge clk)
begin
  case(st[9:8])
  0:dx=16-dx_;
  1:dx=32-dx_;
  2:dx=48-dx_;
  3:dx=64-dx_;
  endcase
  dy=~dy_;
end

always @(posedge clk)
begin
  case(st[3:0])
  0:d=d_zf[0];
  1:d=d_zf[1];
  2:d=d_zf[2];
  3:d=d_zf[3];
  4:d=d_zf[4];
  5:d=d_zf[5];
  6:d=d_zf[6];
  7:d=d_zf[7];
  8:d=d_zf[8];
  9:d=d_zf[9];
 10:d=d_zf[10];
 11:d=d_zf[11];
 12:d=d_zf[12];
 13:d=d_zf[13];
 14:d=d_zf[14];
 15:d=d_zf[15];
  endcase
end

always @(posedge clk)
begin
  case(st[9:4])
   0:d_zf=16648;
   1:d_zf= 8712;
   2:d_zf=10120;
   3:d_zf= 1160;
   4:d_zf= 1980;
   5:d_zf=58504;
   6:d_zf=10120;
   7:d_zf= 9384;
   8:d_zf=12184;
   9:d_zf= 8584;
  10:d_zf=12936;
  11:d_zf= 9352;
  12:d_zf= 2728;
  13:d_zf= 4368;
  14:d_zf=    0;
  15:d_zf=    0;
  16:d_zf=16648;
  17:d_zf= 8712;
  18:d_zf=10120;
  19:d_zf= 1160;
  20:d_zf= 1980;
  21:d_zf=58504;
  22:d_zf=10120;
  23:d_zf= 9384;
  24:d_zf=12184;
  25:d_zf= 8584;
  26:d_zf=12936;
  27:d_zf= 9352;
  28:d_zf= 2728;
  29:d_zf= 4368;
  30:d_zf=    0;
  31:d_zf=    0;
  32:d_zf=  512;
  33:d_zf=  768;
  34:d_zf= 1152;
  35:d_zf= 2112;
  36:d_zf= 4128;
  37:d_zf=12252;
  38:d_zf=49160;
  39:d_zf=    0;
  40:d_zf= 8160;
  41:d_zf= 4128;
  42:d_zf= 4128;
  43:d_zf= 4128;
  44:d_zf= 8160;
  45:d_zf= 4128;
  46:d_zf=    0;
  47:d_zf=    0;
  48:d_zf= 2176;
  49:d_zf= 2176;
  50:d_zf= 4360;
  51:d_zf= 4604;
  52:d_zf=12928;
  53:d_zf=21632;
  54:d_zf=37112;
  55:d_zf= 4224;
  56:d_zf= 4224;
  57:d_zf= 4232;
  58:d_zf= 4348;
  59:d_zf= 4224;
  60:d_zf= 4224;
  61:d_zf= 4224;
  62:d_zf=    0;
  63:d_zf=    0;
  endcase
end

endmodule