module xwjc(clk,s1,s2,d1,d2,d3);
input clk,s1,s2;
output[7:0] d1,d2,d3;   //24位數(shù)據(jù),最高位為相位符號

reg a;
reg[22:0] d,dd;

wire s=s1&s2;
wire[7:0] d1=d[7:0];
wire[7:0] d2=d[15:8];
wire[7:0] d3={a,d[22:16]};

always @(posedge clk)
begin
  dd=s?dd+1:0;
end

always @(negedge s)
begin
  d=dd;
  a=s1;
end 

endmodule