module data_io(data,cs,wr,rd,ale,led);
input cs,wr,rd,ale;
inout[7:0] data;
output[7:0] led;
//output[3:0] xsa;

reg[7:0] d_reg,r1;
//reg[7:0] xs1,xs2,xs3,xs4,xsd;
//reg[3:0] xsa;

wire rd_=cs?0:~rd;
wire wr_=cs?0:~wr;                       //片選
wire[7:0] data=(rd_)?d_reg:8'hzz; 
wire[7:0] led=~r1;
wire[7:0] addr=ale?data:addr;            //地址鎖存

always @(posedge wr_)                    //寫操作
begin
  if(addr==0) r1=data;
end

always @(posedge rd_)                    //讀操作
begin
  if(addr==0) d_reg=r1;
end

endmodule