USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TIMER IS
	PORT( iclk : IN STD_LOGIC;     --input clock
		  iRst : IN STD_LOGIC;
		  iNF:   IN STD_LOGIC;
		  iSMin: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
		  iSHou: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		  oLSec: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
		  oLMin: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
		  oLHou: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
		  oHouR: OUT STD_LOGIC;
		  oRing: OUT STD_LOGIC);
END TIMER;

ARCHITECTURE run OF TIMER IS
	COMPONENT DTIMER
	PORT( iclk : IN STD_LOGIC;     --input clock
		  iRst : IN STD_LOGIC;
		  Ohou:  OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
		  Omin:  OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
		  Osec:  OUT STD_LOGIC_VECTOR(5 DOWNTO 0));
	END COMPONENT;
	COMPONENT DLED
	PORT( 
		  hou:  IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		  min:  IN STD_LOGIC_VECTOR(5 DOWNTO 0);
		  sec:  IN STD_LOGIC_VECTOR(5 DOWNTO 0);
		  oLHou: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
		  oLMin: OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
		  oLSec: OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
	END COMPONENT;
	COMPONENT FTIMER
	PORT( iNF:   IN STD_LOGIC;
		  hou:  IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		  min:  IN STD_LOGIC_VECTOR(5 DOWNTO 0);
		  sec:  IN STD_LOGIC_VECTOR(5 DOWNTO 0);
		  iSMin: IN STD_LOGIC_VECTOR(5 DOWNTO 0);
		  iSHou: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
		  oHouR: OUT STD_LOGIC;
		  oRing: OUT STD_LOGIC);
	END COMPONENT;
	SIGNAL hou : STD_LOGIC_VECTOR(4 DOWNTO 0);
	SIGNAL min : STD_LOGIC_VECTOR(5 DOWNTO 0);
	SIGNAL sec : STD_LOGIC_VECTOR(5 DOWNTO 0);
	BEGIN
	U1: DTIMER PORT MAP(iclk=>iclk, 
						iRst=>iRst, 
						oHou=>hou, 
						oMin=>min, 
						oSec=>sec);
	U2: DLED   PORT MAP(hou=>hou, 
						min=>min, 
						sec=>sec, 
						oLHou=>oLHou, 
						oLMin=>oLMin, 
						oLSec=>oLSec);
	U3: FTIMER PORT MAP(iNF=>iNF,
						hou=>hou,
						min=>min,
						sec=>sec, 
						iSMin=>iSMin, 
						iSHou=>iSHou, 
						oHouR=>oHouR, 
						oRing=>oRing);
	END run;