{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 19 15:40:15 2008 " "Info: Processing started: Mon May 19 15:40:15 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off I2C_FPGA -c I2C_FPGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off I2C_FPGA -c I2C_FPGA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C_FPGA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C_FPGA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_FPGA " "Info: Found entity 1: I2C_FPGA" {  } { { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_test " "Info: Found entity 1: i2c_test" {  } { { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "I2C_FPGA " "Info: Elaborating entity \"I2C_FPGA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "I2C_FPGA " "Warning: Processing legacy GDF or BDF entity \"I2C_FPGA\" with Max+Plus II bus and instance naming rules" {  } { { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c i2c:inst4 " "Info: Elaborating entity \"i2c\" for hierarchy \"i2c:inst4\"" {  } { { "I2C_FPGA.bdf" "inst4" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { -40 624 808 88 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 i2c.v(78) " "Warning (10230): Verilog HDL assignment warning at i2c.v(78): truncated value with size 32 to match size of target (20)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(96) " "Warning (10230): Verilog HDL assignment warning at i2c.v(96): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 96 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(162) " "Info (10264): Verilog HDL Case Statement information at i2c.v(162): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 162 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(238) " "Info (10264): Verilog HDL Case Statement information at i2c.v(238): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 238 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(303) " "Info (10264): Verilog HDL Case Statement information at i2c.v(303): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 303 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(160) " "Info (10264): Verilog HDL Case Statement information at i2c.v(160): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 160 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(384) " "Info (10264): Verilog HDL Case Statement information at i2c.v(384): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 384 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(460) " "Info (10264): Verilog HDL Case Statement information at i2c.v(460): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 460 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(525) " "Info (10264): Verilog HDL Case Statement information at i2c.v(525): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 525 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(600) " "Info (10264): Verilog HDL Case Statement information at i2c.v(600): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 600 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(382) " "Info (10264): Verilog HDL Case Statement information at i2c.v(382): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 382 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 i2c.v(713) " "Warning (10230): Verilog HDL assignment warning at i2c.v(713): truncated value with size 32 to match size of target (12)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 713 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(721) " "Info (10264): Verilog HDL Case Statement information at i2c.v(721): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 721 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(733) " "Warning (10270): Verilog HDL Case Statement warning at i2c.v(733): incomplete case statement has no default case item" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 733 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "seg_data i2c.v(731) " "Warning (10240): Verilog HDL Always Construct warning at i2c.v(731): inferring latch(es) for variable \"seg_data\", which holds its previous value in one or more paths through the always construct" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[0\] i2c.v(731) " "Info (10041): Inferred latch for \"seg_data\[0\]\" at i2c.v(731)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[1\] i2c.v(731) " "Info (10041): Inferred latch for \"seg_data\[1\]\" at i2c.v(731)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}