{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off I2C_FPGA -c I2C_FPGA --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off I2C_FPGA -c I2C_FPGA --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[6\] " "Warning: Node \"i2c:inst4\|seg_data\[6\]\" is a latch" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[5\] " "Warning: Node \"i2c:inst4\|seg_data\[5\]\" is a latch" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[4\] " "Warning: Node \"i2c:inst4\|seg_data\[4\]\" is a latch" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[3\] " "Warning: Node \"i2c:inst4\|seg_data\[3\]\" is a latch" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[2\] " "Warning: Node \"i2c:inst4\|seg_data\[2\]\" is a latch" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[1\] " "Warning: Node \"i2c:inst4\|seg_data\[1\]\" is a latch" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "i2c:inst4\|seg_data\[0\] " "Warning: Node \"i2c:inst4\|seg_data\[0\]\" is a latch" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}