{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register i2c:inst4\|inner_state.fifth register i2c:inst4\|sda_buf 107.56 MHz 9.297 ns Internal " "Info: Clock \"clk\" has Internal fmax of 107.56 MHz between source register \"i2c:inst4\|inner_state.fifth\" and destination register \"i2c:inst4\|sda_buf\" (period= 9.297 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.022 ns + Longest register register " "Info: + Longest register to register delay is 9.022 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c:inst4\|inner_state.fifth 1 REG LCFF_X13_Y6_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y6_N5; Fanout = 6; REG Node = 'i2c:inst4\|inner_state.fifth'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst4|inner_state.fifth } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.539 ns) 0.987 ns i2c:inst4\|Selector14~236 2 COMB LCCOMB_X13_Y6_N8 4 " "Info: 2: + IC(0.448 ns) + CELL(0.539 ns) = 0.987 ns; Loc. = LCCOMB_X13_Y6_N8; Fanout = 4; COMB Node = 'i2c:inst4\|Selector14~236'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.987 ns" { i2c:inst4|inner_state.fifth i2c:inst4|Selector14~236 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 238 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.112 ns) + CELL(0.616 ns) 2.715 ns i2c:inst4\|Selector27~468 3 COMB LCCOMB_X17_Y6_N24 4 " "Info: 3: + IC(1.112 ns) + CELL(0.616 ns) = 2.715 ns; Loc. = LCCOMB_X17_Y6_N24; Fanout = 4; COMB Node = 'i2c:inst4\|Selector27~468'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.728 ns" { i2c:inst4|Selector14~236 i2c:inst4|Selector27~468 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 303 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.486 ns) + CELL(0.366 ns) 4.567 ns i2c:inst4\|Selector27~469 4 COMB LCCOMB_X13_Y7_N12 1 " "Info: 4: + IC(1.486 ns) + CELL(0.366 ns) = 4.567 ns; Loc. = LCCOMB_X13_Y7_N12; Fanout = 1; COMB Node = 'i2c:inst4\|Selector27~469'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.852 ns" { i2c:inst4|Selector27~468 i2c:inst4|Selector27~469 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 303 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.824 ns) + CELL(0.651 ns) 7.042 ns i2c:inst4\|Selector116~637 5 COMB LCCOMB_X13_Y7_N6 1 " "Info: 5: + IC(1.824 ns) + CELL(0.651 ns) = 7.042 ns; Loc. = LCCOMB_X13_Y7_N6; Fanout = 1; COMB Node = 'i2c:inst4\|Selector116~637'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.475 ns" { i2c:inst4|Selector27~469 i2c:inst4|Selector116~637 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.392 ns) + CELL(0.651 ns) 8.085 ns i2c:inst4\|Selector116~642 6 COMB LCCOMB_X13_Y7_N14 1 " "Info: 6: + IC(0.392 ns) + CELL(0.651 ns) = 8.085 ns; Loc. = LCCOMB_X13_Y7_N14; Fanout = 1; COMB Node = 'i2c:inst4\|Selector116~642'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.043 ns" { i2c:inst4|Selector116~637 i2c:inst4|Selector116~642 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 136 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.623 ns) + CELL(0.206 ns) 8.914 ns i2c:inst4\|sda_buf~feeder 7 COMB LCCOMB_X14_Y7_N26 1 " "Info: 7: + IC(0.623 ns) + CELL(0.206 ns) = 8.914 ns; Loc. = LCCOMB_X14_Y7_N26; Fanout = 1; COMB Node = 'i2c:inst4\|sda_buf~feeder'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.829 ns" { i2c:inst4|Selector116~642 i2c:inst4|sda_buf~feeder } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.022 ns i2c:inst4\|sda_buf 8 REG LCFF_X14_Y7_N27 17 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 9.022 ns; Loc. = LCFF_X14_Y7_N27; Fanout = 17; REG Node = 'i2c:inst4\|sda_buf'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { i2c:inst4|sda_buf~feeder i2c:inst4|sda_buf } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.137 ns ( 34.77 % ) " "Info: Total cell delay = 3.137 ns ( 34.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.885 ns ( 65.23 % ) " "Info: Total interconnect delay = 5.885 ns ( 65.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.022 ns" { i2c:inst4|inner_state.fifth i2c:inst4|Selector14~236 i2c:inst4|Selector27~468 i2c:inst4|Selector27~469 i2c:inst4|Selector116~637 i2c:inst4|Selector116~642 i2c:inst4|sda_buf~feeder i2c:inst4|sda_buf } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "9.022 ns" { i2c:inst4|inner_state.fifth {} i2c:inst4|Selector14~236 {} i2c:inst4|Selector27~468 {} i2c:inst4|Selector27~469 {} i2c:inst4|Selector116~637 {} i2c:inst4|Selector116~642 {} i2c:inst4|sda_buf~feeder {} i2c:inst4|sda_buf {} } { 0.000ns 0.448ns 1.112ns 1.486ns 1.824ns 0.392ns 0.623ns 0.000ns } { 0.000ns 0.539ns 0.616ns 0.366ns 0.651ns 0.651ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.760 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'clk'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { -96 -64 104 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 85 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 85; COMB Node = 'clk~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { -96 -64 104 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.666 ns) 2.760 ns i2c:inst4\|sda_buf 3 REG LCFF_X14_Y7_N27 17 " "Info: 3: + IC(0.811 ns) + CELL(0.666 ns) = 2.760 ns; Loc. = LCFF_X14_Y7_N27; Fanout = 17; REG Node = 'i2c:inst4\|sda_buf'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.477 ns" { clk~clkctrl i2c:inst4|sda_buf } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.43 % ) " "Info: Total cell delay = 1.806 ns ( 65.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.954 ns ( 34.57 % ) " "Info: Total interconnect delay = 0.954 ns ( 34.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl i2c:inst4|sda_buf } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} i2c:inst4|sda_buf {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.771 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.771 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'clk'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { -96 -64 104 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 85 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 85; COMB Node = 'clk~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { -96 -64 104 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.666 ns) 2.771 ns i2c:inst4\|inner_state.fifth 3 REG LCFF_X13_Y6_N5 6 " "Info: 3: + IC(0.822 ns) + CELL(0.666 ns) = 2.771 ns; Loc. = LCFF_X13_Y6_N5; Fanout = 6; REG Node = 'i2c:inst4\|inner_state.fifth'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.488 ns" { clk~clkctrl i2c:inst4|inner_state.fifth } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.18 % ) " "Info: Total cell delay = 1.806 ns ( 65.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.965 ns ( 34.82 % ) " "Info: Total interconnect delay = 0.965 ns ( 34.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.771 ns" { clk clk~clkctrl i2c:inst4|inner_state.fifth } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.771 ns" { clk {} clk~combout {} clk~clkctrl {} i2c:inst4|inner_state.fifth {} } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl i2c:inst4|sda_buf } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} i2c:inst4|sda_buf {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.771 ns" { clk clk~clkctrl i2c:inst4|inner_state.fifth } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.771 ns" { clk {} clk~combout {} clk~clkctrl {} i2c:inst4|inner_state.fifth {} } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 41 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.022 ns" { i2c:inst4|inner_state.fifth i2c:inst4|Selector14~236 i2c:inst4|Selector27~468 i2c:inst4|Selector27~469 i2c:inst4|Selector116~637 i2c:inst4|Selector116~642 i2c:inst4|sda_buf~feeder i2c:inst4|sda_buf } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "9.022 ns" { i2c:inst4|inner_state.fifth {} i2c:inst4|Selector14~236 {} i2c:inst4|Selector27~468 {} i2c:inst4|Selector27~469 {} i2c:inst4|Selector116~637 {} i2c:inst4|Selector116~642 {} i2c:inst4|sda_buf~feeder {} i2c:inst4|sda_buf {} } { 0.000ns 0.448ns 1.112ns 1.486ns 1.824ns 0.392ns 0.623ns 0.000ns } { 0.000ns 0.539ns 0.616ns 0.366ns 0.651ns 0.651ns 0.206ns 0.108ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.760 ns" { clk clk~clkctrl i2c:inst4|sda_buf } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.760 ns" { clk {} clk~combout {} clk~clkctrl {} i2c:inst4|sda_buf {} } { 0.000ns 0.000ns 0.143ns 0.811ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.771 ns" { clk clk~clkctrl i2c:inst4|inner_state.fifth } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.771 ns" { clk {} clk~combout {} clk~clkctrl {} i2c:inst4|inner_state.fifth {} } { 0.000ns 0.000ns 0.143ns 0.822ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "write register register i2c_test:inst1\|counter\[1\] i2c_test:inst1\|counter\[3\] 360.1 MHz Internal " "Info: Clock \"write\" Internal fmax is restricted to 360.1 MHz between source register \"i2c_test:inst1\|counter\[1\]\" and destination register \"i2c_test:inst1\|counter\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.564 ns + Longest register register " "Info: + Longest register to register delay is 1.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_test:inst1\|counter\[1\] 1 REG LCFF_X13_Y7_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y7_N3; Fanout = 4; REG Node = 'i2c_test:inst1\|counter\[1\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_test:inst1|counter[1] } "NODE_NAME" } } { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.805 ns) + CELL(0.651 ns) 1.456 ns i2c_test:inst1\|counter\[3\]~64 2 COMB LCCOMB_X13_Y7_N10 1 " "Info: 2: + IC(0.805 ns) + CELL(0.651 ns) = 1.456 ns; Loc. = LCCOMB_X13_Y7_N10; Fanout = 1; COMB Node = 'i2c_test:inst1\|counter\[3\]~64'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.456 ns" { i2c_test:inst1|counter[1] i2c_test:inst1|counter[3]~64 } "NODE_NAME" } } { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.564 ns i2c_test:inst1\|counter\[3\] 3 REG LCFF_X13_Y7_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.564 ns; Loc. = LCFF_X13_Y7_N11; Fanout = 2; REG Node = 'i2c_test:inst1\|counter\[3\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { i2c_test:inst1|counter[3]~64 i2c_test:inst1|counter[3] } "NODE_NAME" } } { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.759 ns ( 48.53 % ) " "Info: Total cell delay = 0.759 ns ( 48.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.805 ns ( 51.47 % ) " "Info: Total interconnect delay = 0.805 ns ( 51.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { i2c_test:inst1|counter[1] i2c_test:inst1|counter[3]~64 i2c_test:inst1|counter[3] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "1.564 ns" { i2c_test:inst1|counter[1] {} i2c_test:inst1|counter[3]~64 {} i2c_test:inst1|counter[3] {} } { 0.000ns 0.805ns 0.000ns } { 0.000ns 0.651ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "write destination 7.118 ns + Shortest register " "Info: + Shortest clock path from clock \"write\" to destination register is 7.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns write 1 CLK PIN_45 11 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_45; Fanout = 11; CLK Node = 'write'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { write } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { 48 -64 104 64 "write" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.036 ns) + CELL(0.370 ns) 3.411 ns delay_reset_block:inst2\|inst4 2 COMB LCCOMB_X19_Y6_N4 4 " "Info: 2: + IC(2.036 ns) + CELL(0.370 ns) = 3.411 ns; Loc. = LCCOMB_X19_Y6_N4; Fanout = 4; COMB Node = 'delay_reset_block:inst2\|inst4'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.406 ns" { write delay_reset_block:inst2|inst4 } "NODE_NAME" } } { "delay_reset_block.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.221 ns) + CELL(0.000 ns) 5.632 ns delay_reset_block:inst2\|inst4~clkctrl 3 COMB CLKCTRL_G5 4 " "Info: 3: + IC(2.221 ns) + CELL(0.000 ns) = 5.632 ns; Loc. = CLKCTRL_G5; Fanout = 4; COMB Node = 'delay_reset_block:inst2\|inst4~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.221 ns" { delay_reset_block:inst2|inst4 delay_reset_block:inst2|inst4~clkctrl } "NODE_NAME" } } { "delay_reset_block.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.666 ns) 7.118 ns i2c_test:inst1\|counter\[3\] 4 REG LCFF_X13_Y7_N11 2 " "Info: 4: + IC(0.820 ns) + CELL(0.666 ns) = 7.118 ns; Loc. = LCFF_X13_Y7_N11; Fanout = 2; REG Node = 'i2c_test:inst1\|counter\[3\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { delay_reset_block:inst2|inst4~clkctrl i2c_test:inst1|counter[3] } "NODE_NAME" } } { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.041 ns ( 28.67 % ) " "Info: Total cell delay = 2.041 ns ( 28.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.077 ns ( 71.33 % ) " "Info: Total interconnect delay = 5.077 ns ( 71.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.118 ns" { write delay_reset_block:inst2|inst4 delay_reset_block:inst2|inst4~clkctrl i2c_test:inst1|counter[3] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "7.118 ns" { write {} write~combout {} delay_reset_block:inst2|inst4 {} delay_reset_block:inst2|inst4~clkctrl {} i2c_test:inst1|counter[3] {} } { 0.000ns 0.000ns 2.036ns 2.221ns 0.820ns } { 0.000ns 1.005ns 0.370ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "write source 7.118 ns - Longest register " "Info: - Longest clock path from clock \"write\" to source register is 7.118 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.005 ns) 1.005 ns write 1 CLK PIN_45 11 " "Info: 1: + IC(0.000 ns) + CELL(1.005 ns) = 1.005 ns; Loc. = PIN_45; Fanout = 11; CLK Node = 'write'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { write } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { 48 -64 104 64 "write" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.036 ns) + CELL(0.370 ns) 3.411 ns delay_reset_block:inst2\|inst4 2 COMB LCCOMB_X19_Y6_N4 4 " "Info: 2: + IC(2.036 ns) + CELL(0.370 ns) = 3.411 ns; Loc. = LCCOMB_X19_Y6_N4; Fanout = 4; COMB Node = 'delay_reset_block:inst2\|inst4'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.406 ns" { write delay_reset_block:inst2|inst4 } "NODE_NAME" } } { "delay_reset_block.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.221 ns) + CELL(0.000 ns) 5.632 ns delay_reset_block:inst2\|inst4~clkctrl 3 COMB CLKCTRL_G5 4 " "Info: 3: + IC(2.221 ns) + CELL(0.000 ns) = 5.632 ns; Loc. = CLKCTRL_G5; Fanout = 4; COMB Node = 'delay_reset_block:inst2\|inst4~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.221 ns" { delay_reset_block:inst2|inst4 delay_reset_block:inst2|inst4~clkctrl } "NODE_NAME" } } { "delay_reset_block.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/delay_reset_block.bdf" { { 208 872 936 256 "inst4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.820 ns) + CELL(0.666 ns) 7.118 ns i2c_test:inst1\|counter\[1\] 4 REG LCFF_X13_Y7_N3 4 " "Info: 4: + IC(0.820 ns) + CELL(0.666 ns) = 7.118 ns; Loc. = LCFF_X13_Y7_N3; Fanout = 4; REG Node = 'i2c_test:inst1\|counter\[1\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.486 ns" { delay_reset_block:inst2|inst4~clkctrl i2c_test:inst1|counter[1] } "NODE_NAME" } } { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.041 ns ( 28.67 % ) " "Info: Total cell delay = 2.041 ns ( 28.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.077 ns ( 71.33 % ) " "Info: Total interconnect delay = 5.077 ns ( 71.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.118 ns" { write delay_reset_block:inst2|inst4 delay_reset_block:inst2|inst4~clkctrl i2c_test:inst1|counter[1] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "7.118 ns" { write {} write~combout {} delay_reset_block:inst2|inst4 {} delay_reset_block:inst2|inst4~clkctrl {} i2c_test:inst1|counter[1] {} } { 0.000ns 0.000ns 2.036ns 2.221ns 0.820ns } { 0.000ns 1.005ns 0.370ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.118 ns" { write delay_reset_block:inst2|inst4 delay_reset_block:inst2|inst4~clkctrl i2c_test:inst1|counter[3] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "7.118 ns" { write {} write~combout {} delay_reset_block:inst2|inst4 {} delay_reset_block:inst2|inst4~clkctrl {} i2c_test:inst1|counter[3] {} } { 0.000ns 0.000ns 2.036ns 2.221ns 0.820ns } { 0.000ns 1.005ns 0.370ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.118 ns" { write delay_reset_block:inst2|inst4 delay_reset_block:inst2|inst4~clkctrl i2c_test:inst1|counter[1] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "7.118 ns" { write {} write~combout {} delay_reset_block:inst2|inst4 {} delay_reset_block:inst2|inst4~clkctrl {} i2c_test:inst1|counter[1] {} } { 0.000ns 0.000ns 2.036ns 2.221ns 0.820ns } { 0.000ns 1.005ns 0.370ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { i2c_test:inst1|counter[1] i2c_test:inst1|counter[3]~64 i2c_test:inst1|counter[3] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "1.564 ns" { i2c_test:inst1|counter[1] {} i2c_test:inst1|counter[3]~64 {} i2c_test:inst1|counter[3] {} } { 0.000ns 0.805ns 0.000ns } { 0.000ns 0.651ns 0.108ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.118 ns" { write delay_reset_block:inst2|inst4 delay_reset_block:inst2|inst4~clkctrl i2c_test:inst1|counter[3] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "7.118 ns" { write {} write~combout {} delay_reset_block:inst2|inst4 {} delay_reset_block:inst2|inst4~clkctrl {} i2c_test:inst1|counter[3] {} } { 0.000ns 0.000ns 2.036ns 2.221ns 0.820ns } { 0.000ns 1.005ns 0.370ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.118 ns" { write delay_reset_block:inst2|inst4 delay_reset_block:inst2|inst4~clkctrl i2c_test:inst1|counter[1] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "7.118 ns" { write {} write~combout {} delay_reset_block:inst2|inst4 {} delay_reset_block:inst2|inst4~clkctrl {} i2c_test:inst1|counter[1] {} } { 0.000ns 0.000ns 2.036ns 2.221ns 0.820ns } { 0.000ns 1.005ns 0.370ns 0.000ns 0.666ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_test:inst1|counter[3] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { i2c_test:inst1|counter[3] {} } {  } {  } "" } } { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}