{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 77 " "Warning: Circuit may not operate. Detected 77 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "i2c:inst4\|readData_reg\[3\] i2c:inst4\|seg_data\[2\] clk 3.87 ns " "Info: Found hold time violation between source  pin or register \"i2c:inst4\|readData_reg\[3\]\" and destination pin or register \"i2c:inst4\|seg_data\[2\]\" for clock \"clk\" (Hold time is 3.87 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "7.144 ns + Largest " "Info: + Largest clock skew is 7.144 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.914 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 9.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'clk'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { -96 -64 104 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.970 ns) 3.459 ns i2c:inst4\|en\[1\] 2 REG LCFF_X8_Y6_N31 7 " "Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.459 ns; Loc. = LCFF_X8_Y6_N31; Fanout = 7; REG Node = 'i2c:inst4\|en\[1\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { clk i2c:inst4|en[1] } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 706 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.829 ns) + CELL(0.370 ns) 6.658 ns i2c:inst4\|WideOr3~64 3 COMB LCCOMB_X8_Y6_N26 1 " "Info: 3: + IC(2.829 ns) + CELL(0.370 ns) = 6.658 ns; Loc. = LCCOMB_X8_Y6_N26; Fanout = 1; COMB Node = 'i2c:inst4\|WideOr3~64'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.199 ns" { i2c:inst4|en[1] i2c:inst4|WideOr3~64 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.753 ns) + CELL(0.000 ns) 8.411 ns i2c:inst4\|WideOr3~64clkctrl 4 COMB CLKCTRL_G1 7 " "Info: 4: + IC(1.753 ns) + CELL(0.000 ns) = 8.411 ns; Loc. = CLKCTRL_G1; Fanout = 7; COMB Node = 'i2c:inst4\|WideOr3~64clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.753 ns" { i2c:inst4|WideOr3~64 i2c:inst4|WideOr3~64clkctrl } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 733 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(0.206 ns) 9.914 ns i2c:inst4\|seg_data\[2\] 5 REG LCCOMB_X7_Y6_N0 1 " "Info: 5: + IC(1.297 ns) + CELL(0.206 ns) = 9.914 ns; Loc. = LCCOMB_X7_Y6_N0; Fanout = 1; REG Node = 'i2c:inst4\|seg_data\[2\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.503 ns" { i2c:inst4|WideOr3~64clkctrl i2c:inst4|seg_data[2] } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 731 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.686 ns ( 27.09 % ) " "Info: Total cell delay = 2.686 ns ( 27.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.228 ns ( 72.91 % ) " "Info: Total interconnect delay = 7.228 ns ( 72.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.914 ns" { clk i2c:inst4|en[1] i2c:inst4|WideOr3~64 i2c:inst4|WideOr3~64clkctrl i2c:inst4|seg_data[2] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "9.914 ns" { clk {} clk~combout {} i2c:inst4|en[1] {} i2c:inst4|WideOr3~64 {} i2c:inst4|WideOr3~64clkctrl {} i2c:inst4|seg_data[2] {} } { 0.000ns 0.000ns 1.349ns 2.829ns 1.753ns 1.297ns } { 0.000ns 1.140ns 0.970ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.770 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 17 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 17; CLK Node = 'clk'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { -96 -64 104 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 85 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 85; COMB Node = 'clk~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { -96 -64 104 -80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.666 ns) 2.770 ns i2c:inst4\|readData_reg\[3\] 3 REG LCFF_X12_Y6_N7 2 " "Info: 3: + IC(0.821 ns) + CELL(0.666 ns) = 2.770 ns; Loc. = LCFF_X12_Y6_N7; Fanout = 2; REG Node = 'i2c:inst4\|readData_reg\[3\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.487 ns" { clk~clkctrl i2c:inst4|readData_reg[3] } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.20 % ) " "Info: Total cell delay = 1.806 ns ( 65.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.964 ns ( 34.80 % ) " "Info: Total interconnect delay = 0.964 ns ( 34.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.770 ns" { clk clk~clkctrl i2c:inst4|readData_reg[3] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.770 ns" { clk {} clk~combout {} clk~clkctrl {} i2c:inst4|readData_reg[3] {} } { 0.000ns 0.000ns 0.143ns 0.821ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.914 ns" { clk i2c:inst4|en[1] i2c:inst4|WideOr3~64 i2c:inst4|WideOr3~64clkctrl i2c:inst4|seg_data[2] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "9.914 ns" { clk {} clk~combout {} i2c:inst4|en[1] {} i2c:inst4|WideOr3~64 {} i2c:inst4|WideOr3~64clkctrl {} i2c:inst4|seg_data[2] {} } { 0.000ns 0.000ns 1.349ns 2.829ns 1.753ns 1.297ns } { 0.000ns 1.140ns 0.970ns 0.370ns 0.000ns 0.206ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.770 ns" { clk clk~clkctrl i2c:inst4|readData_reg[3] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyM