module int_div(clk, reset, div_out);

input clk, reset;
output reg div_out;

reg [31:0] clk_div;

parameter CLK_FREQ = 'D50_000_000;//系統時鐘
parameter DCLK_FREQ = 'D1;        //輸出頻率10Hz

always @(posedge clk) begin
	if (!reset) begin
		clk_div <= 32'h0;
	end
	else begin
		if(clk_div == 32'h17d7840) begin
			clk_div <= 32'h0;
			div_out <= ~div_out;
		end
		else
		begin
			clk_div <= clk_div + 1;
		end
	end
end
endmodule