LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
entity rita is
port(en,clk,lr:in std_logic;
      r2,r1,r0:out std_logic);
end rita;
ARCHITECTURE rit_arc OF rita IS
begin
process(clk,en,lr)
variable tmp:std_logic_vector(2 downto 0);
begin
if lr='1'then
  tmp:="111";
elsif en='0'then
 tmp:="000";
elsif clk'event and clk='1'then
if tmp="000" then
   tmp:="100";
else
  tmp:='0'&tmp(2 downto 1);
end if;
end if;
r2<=tmp(2);
r1<=tmp(1);
r0<=tmp(0);
end process;
end rit_arc;