# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		xulieqi_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY XULIEQI
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:44:35  JULY 09, 2002"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name LL_ROOT_REGION ON -entity xulieqi -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -entity xulieqi -section_id "Root Region"
set_global_assignment -name VHDL_FILE SCHK.vhd
set_global_assignment -name SIMULATION_MODE TIMING
set_global_assignment -name VECTOR_WAVEFORM_FILE SCHK.vwf
set_global_assignment -name VHDL_FILE XULIE.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE XULIE.vwf
set_global_assignment -name VHDL_FILE DECL7S.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE DECL7S.vwf
set_global_assignment -name VHDL_FILE XULIEQI.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE XULIEQI.vwf
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE XULIEQI.vwf
set_location_assignment PIN_G26 -to CLK
set_location_assignment PIN_N23 -to RESET
set_location_assignment PIN_C13 -to DIN8[0]
set_location_assignment PIN_AC13 -to DIN8[1]
set_location_assignment PIN_AD13 -to DIN8[2]
set_location_assignment PIN_AF14 -to DIN8[3]
set_location_assignment PIN_AE14 -to DIN8[4]
set_location_assignment PIN_P25 -to DIN8[5]
set_location_assignment PIN_N26 -to DIN8[6]
set_location_assignment PIN_N25 -to DIN8[7]
set_location_assignment PIN_AF10 -to LED7S[0]
set_location_assignment PIN_AB12 -to LED7S[1]
set_location_assignment PIN_AC12 -to LED7S[2]
set_location_assignment PIN_AD11 -to LED7S[3]
set_location_assignment PIN_AE11 -to LED7S[4]
set_location_assignment PIN_V14 -to LED7S[5]
set_location_assignment PIN_V13 -to LED7S[6]