LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CNT1 IS
  PORT(clk6:IN STD_LOGIC;
       Q6: OUT STD_LOGIC);
END CNT1;

ARCHITECTURE ddy OF CNT1 IS
SIGNAL s:STD_LOGIC;
SIGNAL mi:INTEGER RANGE 1 TO 13500;
BEGIN
PROCESS(clk6)
BEGIN
    IF (clk6'EVENT AND clk6='1') THEN
        IF(MI=13500) THEN
			MI<=1;
			S<=NOT S;
			ELSIF(MI<13500) THEN
			    MI<=MI+1;
				ELSIF(MI=6750) THEN
					S<=NOT S;		
		END IF;
	Q6<=S;
    END IF;
END PROCESS;
END ddy;