## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-Translate Simulation
##
vlib work
## Compile Post-Translate Model for Module can_top
vcom -87 -explicit  can_top_translate.vhd
vlog  can_testbench.v
vsim -t 1ps    -lib work can_testbench
do can_testbench.udo
view wave
add wave *
view structure
view signals
run 1000ns
## End