?? de2_ccd_pip.map.rpt
字號:
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; Maximum DSP Block Usage ; -1 ; -1 ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
+--------------------------------------------------------------------+--------------------+--------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+-------------------------------------------+-----------------+------------------------------+--------------------------------------------------------------------------+
; VGA_Param.h ; yes ; User File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/VGA_Param.h ;
; VGA_Controller.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/VGA_Controller.v ;
; I2C_CCD_Config.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/I2C_CCD_Config.v ;
; I2C_Controller.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/I2C_Controller.v ;
; Line_Buffer.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Line_Buffer.v ;
; Reset_Delay.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Reset_Delay.v ;
; SEG7_LUT.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/SEG7_LUT.v ;
; SEG7_LUT_8.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/SEG7_LUT_8.v ;
; Sdram_Control_4Port/command.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Sdram_Control_4Port/command.v ;
; Sdram_Control_4Port/control_interface.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Sdram_Control_4Port/control_interface.v ;
; Sdram_Control_4Port/sdr_data_path.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Sdram_Control_4Port/sdr_data_path.v ;
; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Sdram_Control_4Port/Sdram_Control_4Port.v ;
; Sdram_Control_4Port/Sdram_FIFO.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Sdram_Control_4Port/Sdram_FIFO.v ;
; Sdram_Control_4Port/Sdram_PLL.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Sdram_Control_4Port/Sdram_PLL.v ;
; CCD_Capture.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/CCD_Capture.v ;
; RAW2RGB_2X.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/RAW2RGB_2X.v ;
; RAW2RGB_4X.v ; yes ; User Verilog HDL File ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/RAW2RGB_4X.v ;
; Sdram_Control_4Port/Sdram_Params.h ; yes ; Other ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/Sdram_Control_4Port/Sdram_Params.h ;
; DE2_CCD_PIP.v ; yes ; Other ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/DE2_CCD_PIP.v ;
; altshift_taps.tdf ; yes ; Megafunction ; c:/altera/quartus51/libraries/megafunctions/altshift_taps.tdf ;
; altdpram.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/altdpram.inc ;
; lpm_counter.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/lpm_counter.inc ;
; lpm_compare.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/lpm_compare.inc ;
; lpm_constant.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/lpm_constant.inc ;
; db/shift_taps_jei.tdf ; yes ; Auto-Generated Megafunction ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/db/shift_taps_jei.tdf ;
; db/altsyncram_ohv.tdf ; yes ; Auto-Generated Megafunction ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/db/altsyncram_ohv.tdf ;
; db/cntr_1tc.tdf ; yes ; Auto-Generated Megafunction ; C:/DE2/DE2_CCD_new/DE2_CCD_PIP/db/cntr_1tc.tdf ;
; altpll.tdf ; yes ; Megafunction ; c:/altera/quartus51/libraries/megafunctions/altpll.tdf ;
; aglobal51.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/aglobal51.inc ;
; stratix_pll.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/stratix_pll.inc ;
; stratixii_pll.inc ; yes ; Other ; c:/altera/quartus51/libraries/megafunctions/stratixii_pll.inc ;
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