--G1_SA[8] is Sdram_Control_4Port:u6|SA[8]
G1_SA[8] = DFFEAS(G1L84, MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[9] is Sdram_Control_4Port:u6|SA[9]
G1_SA[9] = DFFEAS(G1L85, MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[10] is Sdram_Control_4Port:u6|SA[10]
G1_SA[10] = DFFEAS(G1L86, MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_SA[11] is Sdram_Control_4Port:u6|SA[11]
G1_SA[11] = DFFEAS(G1L87, MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_DQM[1] is Sdram_Control_4Port:u6|DQM[1]
G1_DQM[1] = DFFEAS(G1L14, MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_WE_N is Sdram_Control_4Port:u6|WE_N
G1_WE_N = DFFEAS(G1L116, MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_CAS_N is Sdram_Control_4Port:u6|CAS_N
G1_CAS_N = DFFEAS(G1L5, MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_RAS_N is Sdram_Control_4Port:u6|RAS_N
G1_RAS_N = DFFEAS(G1L50, MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_CS_N[0] is Sdram_Control_4Port:u6|CS_N[0]
G1_CS_N[0] = DFFEAS(T1_CS_N[0], MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_BA[0] is Sdram_Control_4Port:u6|BA[0]
G1_BA[0] = DFFEAS(T1_BA[0], MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--G1_BA[1] is Sdram_Control_4Port:u6|BA[1]
G1_BA[1] = DFFEAS(T1_BA[1], MB1__clk0,  ,  ,  ,  ,  ,  ,  );


--MB1__clk0 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0
MB1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());

--MB1__clk1 is Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1
MB1__clk1 = PLL.CLK1(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLOCK_50), .INCLK());


--CCD1_MCLK is CCD1_MCLK
CCD1_MCLK = DFFEAS(A1L8, CLOCK_50,  ,  ,  ,  ,  ,  ,  );


--B1_oVGA_H_SYNC is VGA_Controller:u1|oVGA_H_SYNC
B1_oVGA_H_SYNC = DFFEAS(B1L43, CCD1_MCLK, C1_oRST_2,  ,  ,  ,  ,  ,  );


--B1_oVGA_V_SYNC is VGA_Controller:u1|oVGA_V_SYNC
B1_oVGA_V_SYNC = DFFEAS(B1L158, CCD1_MCLK, C1_oRST_2,  ,  ,  ,  ,  ,  );


--B1_oVGA_BLANK is VGA_Controller:u1|oVGA_BLANK
B1_oVGA_BLANK = B1_oVGA_H_SYNC & B1_oVGA_V_SYNC;


--B1_H_Cont[4] is VGA_Controller:u1|H_Cont[4]
B1_H_Cont[4] = DFFEAS(B1L20, CCD1_MCLK, C1_oRST_2,  ,  ,  ,  , B1L44,  );


--B1_H_Cont[5] is VGA_Controller:u1|H_Cont[5]
B1_H_Cont[5] = DFFEAS(B1L23, CCD1_MCLK, C1_oRST_2,  ,  ,  ,  , B1L44,  );


--B1_H_Cont[6] is VGA_Controller:u1|H_Cont[6]
B1_H_Cont[6] = DFFEAS(B1L27, CCD1_MCLK, C1_oRST_2,  ,  ,  ,  , B1L44,  );


--B1L1 is VGA_Controller:u1|Equal~115
B1L1 = !B1_H_Cont[4] & !B1_H_Cont[5] & !B1_H_Cont[6];


--B1_H_Cont[7] is VGA_Controller:u1|H_Cont[7]
B1_H_Cont[7] = DFFEAS(B1L30, CCD1_MCLK, C1_oRST_2,  ,  ,  ,  , B1L44,  );


--B1_H_Cont[8] is VGA_Controller:u1|H_Cont[8]
B1_H_Cont[8] = DFFEAS(B1L33, CCD1_MCLK, C1_oRST_2,  ,  ,  ,  , B1L44,  );


--B1_H_Cont[9] is VGA_Controller:u1|H_Cont[9]
B1_H_Cont[9] = DFFEAS(B1L36, CCD1_MCLK, C1_oRST_2,  ,  ,  ,  , B1L44,  );


--B1L155 is VGA_Controller:u1|oVGA_R~876
B1L155 = B1_H_Cont[8] & (B1L1 & !B1_H_Cont[7] # !B1_H_Cont[9]) # !B1_H_Cont[8] & (B1_H_Cont[9] # !B1L1 & B1_H_Cont[7]);


--B1_V_Cont[9] is VGA_Controller:u1|V_Cont[9]
B1_V_Cont[9] = DFFEAS(B1L77, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1_V_Cont[1] is VGA_Controller:u1|V_Cont[1]
B1_V_Cont[1] = DFFEAS(B1L53, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1_V_Cont[2] is VGA_Controller:u1|V_Cont[2]
B1_V_Cont[2] = DFFEAS(B1L56, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1_V_Cont[3] is VGA_Controller:u1|V_Cont[3]
B1_V_Cont[3] = DFFEAS(B1L59, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1_V_Cont[6] is VGA_Controller:u1|V_Cont[6]
B1_V_Cont[6] = DFFEAS(B1L68, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1_V_Cont[7] is VGA_Controller:u1|V_Cont[7]
B1_V_Cont[7] = DFFEAS(B1L71, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1_V_Cont[8] is VGA_Controller:u1|V_Cont[8]
B1_V_Cont[8] = DFFEAS(B1L74, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1L38 is VGA_Controller:u1|LessThan~1087
B1L38 = !B1_V_Cont[6] & !B1_V_Cont[7] & !B1_V_Cont[8];


--B1_V_Cont[4] is VGA_Controller:u1|V_Cont[4]
B1_V_Cont[4] = DFFEAS(B1L62, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1_V_Cont[5] is VGA_Controller:u1|V_Cont[5]
B1_V_Cont[5] = DFFEAS(B1L65, CCD1_MCLK, C1_oRST_2,  , B1L5,  ,  , B1L46,  );


--B1L39 is VGA_Controller:u1|LessThan~1088
B1L39 = B1L38 & !B1_V_Cont[4] & !B1_V_Cont[5];


--B1L40 is VGA_Controller:u1|LessThan~1089
B1L40 = B1_V_Cont[1] # B1_V_Cont[2] # B1_V_Cont[3] # !B1L39;


--B1L41 is VGA_Controller:u1|LessThan~1090
B1L41 = !B1_V_Cont[4] & !B1_V_Cont[1] & !B1_V_Cont[2] & !B1_V_Cont[3];


--B1L42 is VGA_Controller:u1|LessThan~1091
B1L42 = B1L38 & !B1_V_Cont[9] & (B1L41 # !B1_V_Cont[5]);


--B1L156 is VGA_Controller:u1|oVGA_R~877
B1L156 = B1L155 & !B1L42 & (!B1L40 # !B1_V_Cont[9]);


--JB4_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB4_q_a[10]_PORT_A_data_in = VCC;
JB4_q_a[10]_PORT_A_data_in_reg = DFFE(JB4_q_a[10]_PORT_A_data_in, JB4_q_a[10]_clock_0, , , JB4_q_a[10]_clock_enable_0);
JB4_q_a[10]_PORT_B_data_in = G1_mDATAOUT[10];
JB4_q_a[10]_PORT_B_data_in_reg = DFFE(JB4_q_a[10]_PORT_B_data_in, JB4_q_a[10]_clock_1, , , JB4_q_a[10]_clock_enable_1);
JB4_q_a[10]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[10]_PORT_A_address_reg = DFFE(JB4_q_a[10]_PORT_A_address, JB4_q_a[10]_clock_0, , , JB4_q_a[10]_clock_enable_0);
JB4_q_a[10]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[10]_PORT_B_address_reg = DFFE(JB4_q_a[10]_PORT_B_address, JB4_q_a[10]_clock_1, , , JB4_q_a[10]_clock_enable_1);
JB4_q_a[10]_PORT_A_write_enable = GND;
JB4_q_a[10]_PORT_A_write_enable_reg = DFFE(JB4_q_a[10]_PORT_A_write_enable, JB4_q_a[10]_clock_0, , , JB4_q_a[10]_clock_enable_0);
JB4_q_a[10]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[10]_PORT_B_write_enable_reg = DFFE(JB4_q_a[10]_PORT_B_write_enable, JB4_q_a[10]_clock_1, , , JB4_q_a[10]_clock_enable_1);
JB4_q_a[10]_clock_0 = CCD1_MCLK;
JB4_q_a[10]_clock_1 = MB1__clk0;
JB4_q_a[10]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[10]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[10]_clear_1 = !C1_oRST_0;
JB4_q_a[10]_PORT_A_data_out = MEMORY(JB4_q_a[10]_PORT_A_data_in_reg, JB4_q_a[10]_PORT_B_data_in_reg, JB4_q_a[10]_PORT_A_address_reg, JB4_q_a[10]_PORT_B_address_reg, JB4_q_a[10]_PORT_A_write_enable_reg, JB4_q_a[10]_PORT_B_write_enable_reg, , , JB4_q_a[10]_clock_0, JB4_q_a[10]_clock_1, JB4_q_a[10]_clock_enable_0, JB4_q_a[10]_clock_enable_1, , JB4_q_a[10]_clear_1);
JB4_q_a[10]_PORT_A_data_out_reg = DFFE(JB4_q_a[10]_PORT_A_data_out, JB4_q_a[10]_clock_0, JB4_q_a[10]_clear_1, , JB4_q_a[10]_clock_enable_0);
JB4_q_a[10] = JB4_q_a[10]_PORT_A_data_out_reg[0];


--JB3_q_a[10] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[10]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB3_q_a[10]_PORT_A_data_in = VCC;
JB3_q_a[10]_PORT_A_data_in_reg = DFFE(JB3_q_a[10]_PORT_A_data_in, JB3_q_a[10]_clock_0, , , JB3_q_a[10]_clock_enable_0);
JB3_q_a[10]_PORT_B_data_in = G1_mDATAOUT[10];
JB3_q_a[10]_PORT_B_data_in_reg = DFFE(JB3_q_a[10]_PORT_B_data_in, JB3_q_a[10]_clock_1, , , JB3_q_a[10]_clock_enable_1);
JB3_q_a[10]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[10]_PORT_A_address_reg = DFFE(JB3_q_a[10]_PORT_A_address, JB3_q_a[10]_clock_0, , , JB3_q_a[10]_clock_enable_0);
JB3_q_a[10]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[10]_PORT_B_address_reg = DFFE(JB3_q_a[10]_PORT_B_address, JB3_q_a[10]_clock_1, , , JB3_q_a[10]_clock_enable_1);
JB3_q_a[10]_PORT_A_write_enable = GND;
JB3_q_a[10]_PORT_A_write_enable_reg = DFFE(JB3_q_a[10]_PORT_A_write_enable, JB3_q_a[10]_clock_0, , , JB3_q_a[10]_clock_enable_0);
JB3_q_a[10]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[10]_PORT_B_write_enable_reg = DFFE(JB3_q_a[10]_PORT_B_write_enable, JB3_q_a[10]_clock_1, , , JB3_q_a[10]_clock_enable_1);
JB3_q_a[10]_clock_0 = CCD1_MCLK;
JB3_q_a[10]_clock_1 = MB1__clk0;
JB3_q_a[10]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[10]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[10]_clear_1 = !C1_oRST_0;
JB3_q_a[10]_PORT_A_data_out = MEMORY(JB3_q_a[10]_PORT_A_data_in_reg, JB3_q_a[10]_PORT_B_data_in_reg, JB3_q_a[10]_PORT_A_address_reg, JB3_q_a[10]_PORT_B_address_reg, JB3_q_a[10]_PORT_A_write_enable_reg, JB3_q_a[10]_PORT_B_write_enable_reg, , , JB3_q_a[10]_clock_0, JB3_q_a[10]_clock_1, JB3_q_a[10]_clock_enable_0, JB3_q_a[10]_clock_enable_1, , JB3_q_a[10]_clear_1);
JB3_q_a[10]_PORT_A_data_out_reg = DFFE(JB3_q_a[10]_PORT_A_data_out, JB3_q_a[10]_clock_0, JB3_q_a[10]_clear_1, , JB3_q_a[10]_clock_enable_0);
JB3_q_a[10] = JB3_q_a[10]_PORT_A_data_out_reg[0];


--B1_oCoord_Y[9] is VGA_Controller:u1|oCoord_Y[9]
B1_oCoord_Y[9] = DFFEAS(B1L135, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );