--B1_oCoord_Y[6] is VGA_Controller:u1|oCoord_Y[6]
B1_oCoord_Y[6] = DFFEAS(B1L126, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[7] is VGA_Controller:u1|oCoord_Y[7]
B1_oCoord_Y[7] = DFFEAS(B1L129, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--Z4L32 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq~68
Z4L32 = B1_oCoord_Y[6] & B1_oCoord_Y[7];


--B1_oCoord_Y[8] is VGA_Controller:u1|oCoord_Y[8]
B1_oCoord_Y[8] = DFFEAS(B1L132, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[4] is VGA_Controller:u1|oCoord_Y[4]
B1_oCoord_Y[4] = DFFEAS(B1L120, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[5] is VGA_Controller:u1|oCoord_Y[5]
B1_oCoord_Y[5] = DFFEAS(B1L123, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[1] is VGA_Controller:u1|oCoord_Y[1]
B1_oCoord_Y[1] = DFFEAS(B1L111, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[2] is VGA_Controller:u1|oCoord_Y[2]
B1_oCoord_Y[2] = DFFEAS(B1L114, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_Y[3] is VGA_Controller:u1|oCoord_Y[3]
B1_oCoord_Y[3] = DFFEAS(B1L117, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--Z4L33 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq~69
Z4L33 = B1_oCoord_Y[3] # B1_oCoord_Y[1] & B1_oCoord_Y[2];


--Z4L34 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq~70
Z4L34 = B1_oCoord_Y[8] & (B1_oCoord_Y[5] # B1_oCoord_Y[4] & Z4L33) # !B1_oCoord_Y[8] & B1_oCoord_Y[5] & (B1_oCoord_Y[4] # Z4L33);


--Z4L35 is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|valid_rdreq~71
Z4L35 = !B1_oCoord_Y[9] & (B1_oCoord_Y[8] $ (Z4L32 & Z4L34));


--B1_oCoord_X[9] is VGA_Controller:u1|oCoord_X[9]
B1_oCoord_X[9] = DFFEAS(B1L107, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[8] is VGA_Controller:u1|oCoord_X[8]
B1_oCoord_X[8] = DFFEAS(B1L104, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[7] is VGA_Controller:u1|oCoord_X[7]
B1_oCoord_X[7] = DFFEAS(B1L101, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--A1L345 is LessThan~972
A1L345 = !B1_oCoord_X[8] & !B1_oCoord_X[7];


--B1_oCoord_X[6] is VGA_Controller:u1|oCoord_X[6]
B1_oCoord_X[6] = DFFEAS(B1L98, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[3] is VGA_Controller:u1|oCoord_X[3]
B1_oCoord_X[3] = DFFEAS(B1L89, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[4] is VGA_Controller:u1|oCoord_X[4]
B1_oCoord_X[4] = DFFEAS(B1L92, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--B1_oCoord_X[5] is VGA_Controller:u1|oCoord_X[5]
B1_oCoord_X[5] = DFFEAS(B1L95, CCD1_MCLK, C1_oRST_2,  , B1L80,  ,  ,  ,  );


--A1L384 is Pre_Read~186
A1L384 = B1_oCoord_X[3] & B1_oCoord_X[4] & B1_oCoord_X[5];


--A1L385 is Pre_Read~187
A1L385 = B1_oCoord_X[9] & A1L345 & (!A1L384 # !B1_oCoord_X[6]);


--A1L346 is LessThan~973
A1L346 = !B1_oCoord_X[6] & !B1_oCoord_X[7];


--A1L386 is Pre_Read~188
A1L386 = B1_oCoord_X[8] & !B1_oCoord_X[9] & (A1L384 # !A1L346);


--A1L387 is Pre_Read~189
A1L387 = Z4L35 & (A1L385 # A1L386);


--B1L150 is VGA_Controller:u1|oVGA_R[5]~878
B1L150 = B1L156 & (A1L387 & JB4_q_a[10] # !A1L387 & (JB3_q_a[10]));


--JB4_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB4_q_a[11]_PORT_A_data_in = VCC;
JB4_q_a[11]_PORT_A_data_in_reg = DFFE(JB4_q_a[11]_PORT_A_data_in, JB4_q_a[11]_clock_0, , , JB4_q_a[11]_clock_enable_0);
JB4_q_a[11]_PORT_B_data_in = G1_mDATAOUT[11];
JB4_q_a[11]_PORT_B_data_in_reg = DFFE(JB4_q_a[11]_PORT_B_data_in, JB4_q_a[11]_clock_1, , , JB4_q_a[11]_clock_enable_1);
JB4_q_a[11]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[11]_PORT_A_address_reg = DFFE(JB4_q_a[11]_PORT_A_address, JB4_q_a[11]_clock_0, , , JB4_q_a[11]_clock_enable_0);
JB4_q_a[11]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[11]_PORT_B_address_reg = DFFE(JB4_q_a[11]_PORT_B_address, JB4_q_a[11]_clock_1, , , JB4_q_a[11]_clock_enable_1);
JB4_q_a[11]_PORT_A_write_enable = GND;
JB4_q_a[11]_PORT_A_write_enable_reg = DFFE(JB4_q_a[11]_PORT_A_write_enable, JB4_q_a[11]_clock_0, , , JB4_q_a[11]_clock_enable_0);
JB4_q_a[11]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[11]_PORT_B_write_enable_reg = DFFE(JB4_q_a[11]_PORT_B_write_enable, JB4_q_a[11]_clock_1, , , JB4_q_a[11]_clock_enable_1);
JB4_q_a[11]_clock_0 = CCD1_MCLK;
JB4_q_a[11]_clock_1 = MB1__clk0;
JB4_q_a[11]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[11]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[11]_clear_1 = !C1_oRST_0;
JB4_q_a[11]_PORT_A_data_out = MEMORY(JB4_q_a[11]_PORT_A_data_in_reg, JB4_q_a[11]_PORT_B_data_in_reg, JB4_q_a[11]_PORT_A_address_reg, JB4_q_a[11]_PORT_B_address_reg, JB4_q_a[11]_PORT_A_write_enable_reg, JB4_q_a[11]_PORT_B_write_enable_reg, , , JB4_q_a[11]_clock_0, JB4_q_a[11]_clock_1, JB4_q_a[11]_clock_enable_0, JB4_q_a[11]_clock_enable_1, , JB4_q_a[11]_clear_1);
JB4_q_a[11]_PORT_A_data_out_reg = DFFE(JB4_q_a[11]_PORT_A_data_out, JB4_q_a[11]_clock_0, JB4_q_a[11]_clear_1, , JB4_q_a[11]_clock_enable_0);
JB4_q_a[11] = JB4_q_a[11]_PORT_A_data_out_reg[0];


--JB3_q_a[11] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[11]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB3_q_a[11]_PORT_A_data_in = VCC;
JB3_q_a[11]_PORT_A_data_in_reg = DFFE(JB3_q_a[11]_PORT_A_data_in, JB3_q_a[11]_clock_0, , , JB3_q_a[11]_clock_enable_0);
JB3_q_a[11]_PORT_B_data_in = G1_mDATAOUT[11];
JB3_q_a[11]_PORT_B_data_in_reg = DFFE(JB3_q_a[11]_PORT_B_data_in, JB3_q_a[11]_clock_1, , , JB3_q_a[11]_clock_enable_1);
JB3_q_a[11]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[11]_PORT_A_address_reg = DFFE(JB3_q_a[11]_PORT_A_address, JB3_q_a[11]_clock_0, , , JB3_q_a[11]_clock_enable_0);
JB3_q_a[11]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[11]_PORT_B_address_reg = DFFE(JB3_q_a[11]_PORT_B_address, JB3_q_a[11]_clock_1, , , JB3_q_a[11]_clock_enable_1);
JB3_q_a[11]_PORT_A_write_enable = GND;
JB3_q_a[11]_PORT_A_write_enable_reg = DFFE(JB3_q_a[11]_PORT_A_write_enable, JB3_q_a[11]_clock_0, , , JB3_q_a[11]_clock_enable_0);
JB3_q_a[11]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[11]_PORT_B_write_enable_reg = DFFE(JB3_q_a[11]_PORT_B_write_enable, JB3_q_a[11]_clock_1, , , JB3_q_a[11]_clock_enable_1);
JB3_q_a[11]_clock_0 = CCD1_MCLK;
JB3_q_a[11]_clock_1 = MB1__clk0;
JB3_q_a[11]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[11]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[11]_clear_1 = !C1_oRST_0;
JB3_q_a[11]_PORT_A_data_out = MEMORY(JB3_q_a[11]_PORT_A_data_in_reg, JB3_q_a[11]_PORT_B_data_in_reg, JB3_q_a[11]_PORT_A_address_reg, JB3_q_a[11]_PORT_B_address_reg, JB3_q_a[11]_PORT_A_write_enable_reg, JB3_q_a[11]_PORT_B_write_enable_reg, , , JB3_q_a[11]_clock_0, JB3_q_a[11]_clock_1, JB3_q_a[11]_clock_enable_0, JB3_q_a[11]_clock_enable_1, , JB3_q_a[11]_clear_1);
JB3_q_a[11]_PORT_A_data_out_reg = DFFE(JB3_q_a[11]_PORT_A_data_out, JB3_q_a[11]_clock_0, JB3_q_a[11]_clear_1, , JB3_q_a[11]_clock_enable_0);
JB3_q_a[11] = JB3_q_a[11]_PORT_A_data_out_reg[0];


--B1L151 is VGA_Controller:u1|oVGA_R[6]~879
B1L151 = B1L156 & (A1L387 & JB4_q_a[11] # !A1L387 & (JB3_q_a[11]));


--JB4_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB4_q_a[12]_PORT_A_data_in = VCC;
JB4_q_a[12]_PORT_A_data_in_reg = DFFE(JB4_q_a[12]_PORT_A_data_in, JB4_q_a[12]_clock_0, , , JB4_q_a[12]_clock_enable_0);
JB4_q_a[12]_PORT_B_data_in = G1_mDATAOUT[12];
JB4_q_a[12]_PORT_B_data_in_reg = DFFE(JB4_q_a[12]_PORT_B_data_in, JB4_q_a[12]_clock_1, , , JB4_q_a[12]_clock_enable_1);
JB4_q_a[12]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[12]_PORT_A_address_reg = DFFE(JB4_q_a[12]_PORT_A_address, JB4_q_a[12]_clock_0, , , JB4_q_a[12]_clock_enable_0);
JB4_q_a[12]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[12]_PORT_B_address_reg = DFFE(JB4_q_a[12]_PORT_B_address, JB4_q_a[12]_clock_1, , , JB4_q_a[12]_clock_enable_1);
JB4_q_a[12]_PORT_A_write_enable = GND;
JB4_q_a[12]_PORT_A_write_enable_reg = DFFE(JB4_q_a[12]_PORT_A_write_enable, JB4_q_a[12]_clock_0, , , JB4_q_a[12]_clock_enable_0);
JB4_q_a[12]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[12]_PORT_B_write_enable_reg = DFFE(JB4_q_a[12]_PORT_B_write_enable, JB4_q_a[12]_clock_1, , , JB4_q_a[12]_clock_enable_1);
JB4_q_a[12]_clock_0 = CCD1_MCLK;
JB4_q_a[12]_clock_1 = MB1__clk0;
JB4_q_a[12]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[12]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[12]_clear_1 = !C1_oRST_0;
JB4_q_a[12]_PORT_A_data_out = MEMORY(JB4_q_a[12]_PORT_A_data_in_reg, JB4_q_a[12]_PORT_B_data_in_reg, JB4_q_a[12]_PORT_A_address_reg, JB4_q_a[12]_PORT_B_address_reg, JB4_q_a[12]_PORT_A_write_enable_reg, JB4_q_a[12]_PORT_B_write_enable_reg, , , JB4_q_a[12]_clock_0, JB4_q_a[12]_clock_1, JB4_q_a[12]_clock_enable_0, JB4_q_a[12]_clock_enable_1, , JB4_q_a[12]_clear_1);
JB4_q_a[12]_PORT_A_data_out_reg = DFFE(JB4_q_a[12]_PORT_A_data_out, JB4_q_a[12]_clock_0, JB4_q_a[12]_clear_1, , JB4_q_a[12]_clock_enable_0);
JB4_q_a[12] = JB4_q_a[12]_PORT_A_data_out_reg[0];


--JB3_q_a[12] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[12]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB3_q_a[12]_PORT_A_data_in = VCC;
JB3_q_a[12]_PORT_A_data_in_reg = DFFE(JB3_q_a[12]_PORT_A_data_in, JB3_q_a[12]_clock_0, , , JB3_q_a[12]_clock_enable_0);
JB3_q_a[12]_PORT_B_data_in = G1_mDATAOUT[12];
JB3_q_a[12]_PORT_B_data_in_reg = DFFE(JB3_q_a[12]_PORT_B_data_in, JB3_q_a[12]_clock_1, , , JB3_q_a[12]_clock_enable_1);
JB3_q_a[12]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[12]_PORT_A_address_reg = DFFE(JB3_q_a[12]_PORT_A_address, JB3_q_a[12]_clock_0, , , JB3_q_a[12]_clock_enable_0);
JB3_q_a[12]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[12]_PORT_B_address_reg = DFFE(JB3_q_a[12]_PORT_B_address, JB3_q_a[12]_clock_1, , , JB3_q_a[12]_clock_enable_1);
JB3_q_a[12]_PORT_A_write_enable = GND;
JB3_q_a[12]_PORT_A_write_enable_reg = DFFE(JB3_q_a[12]_PORT_A_write_enable, JB3_q_a[12]_clock_0, , , JB3_q_a[12]_clock_enable_0);
JB3_q_a[12]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[12]_PORT_B_write_enable_reg = DFFE(JB3_q_a[12]_PORT_B_write_enable, JB3_q_a[12]_clock_1, , , JB3_q_a[12]_clock_enable_1);
JB3_q_a[12]_clock_0 = CCD1_MCLK;
JB3_q_a[12]_clock_1 = MB1__clk0;
JB3_q_a[12]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[12]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[12]_clear_1 = !C1_oRST_0;
JB3_q_a[12]_PORT_A_data_out = MEMORY(JB3_q_a[12]_PORT_A_data_in_reg, JB3_q_a[12]_PORT_B_data_in_reg, JB3_q_a[12]_PORT_A_address_reg, JB3_q_a[12]_PORT_B_address_reg, JB3_q_a[12]_PORT_A_write_enable_reg, JB3_q_a[12]_PORT_B_write_enable_reg, , , JB3_q_a[12]_clock_0, JB3_q_a[12]_clock_1, JB3_q_a[12]_clock_enable_0, JB3_q_a[12]_clock_enable_1, , JB3_q_a[12]_clear_1);
JB3_q_a[12]_PORT_A_data_out_reg = DFFE(JB3_q_a[12]_PORT_A_data_out, JB3_q_a[12]_clock_0, JB3_q_a[12]_clear_1, , JB3_q_a[12]_clock_enable_0);
JB3_q_a[12] = JB3_q_a[12]_PORT_A_data_out_reg[0];