--B1L152 is VGA_Controller:u1|oVGA_R[7]~880
B1L152 = B1L156 & (A1L387 & JB4_q_a[12] # !A1L387 & (JB3_q_a[12]));


--JB4_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB4_q_a[13]_PORT_A_data_in = VCC;
JB4_q_a[13]_PORT_A_data_in_reg = DFFE(JB4_q_a[13]_PORT_A_data_in, JB4_q_a[13]_clock_0, , , JB4_q_a[13]_clock_enable_0);
JB4_q_a[13]_PORT_B_data_in = G1_mDATAOUT[13];
JB4_q_a[13]_PORT_B_data_in_reg = DFFE(JB4_q_a[13]_PORT_B_data_in, JB4_q_a[13]_clock_1, , , JB4_q_a[13]_clock_enable_1);
JB4_q_a[13]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[13]_PORT_A_address_reg = DFFE(JB4_q_a[13]_PORT_A_address, JB4_q_a[13]_clock_0, , , JB4_q_a[13]_clock_enable_0);
JB4_q_a[13]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[13]_PORT_B_address_reg = DFFE(JB4_q_a[13]_PORT_B_address, JB4_q_a[13]_clock_1, , , JB4_q_a[13]_clock_enable_1);
JB4_q_a[13]_PORT_A_write_enable = GND;
JB4_q_a[13]_PORT_A_write_enable_reg = DFFE(JB4_q_a[13]_PORT_A_write_enable, JB4_q_a[13]_clock_0, , , JB4_q_a[13]_clock_enable_0);
JB4_q_a[13]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[13]_PORT_B_write_enable_reg = DFFE(JB4_q_a[13]_PORT_B_write_enable, JB4_q_a[13]_clock_1, , , JB4_q_a[13]_clock_enable_1);
JB4_q_a[13]_clock_0 = CCD1_MCLK;
JB4_q_a[13]_clock_1 = MB1__clk0;
JB4_q_a[13]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[13]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[13]_clear_1 = !C1_oRST_0;
JB4_q_a[13]_PORT_A_data_out = MEMORY(JB4_q_a[13]_PORT_A_data_in_reg, JB4_q_a[13]_PORT_B_data_in_reg, JB4_q_a[13]_PORT_A_address_reg, JB4_q_a[13]_PORT_B_address_reg, JB4_q_a[13]_PORT_A_write_enable_reg, JB4_q_a[13]_PORT_B_write_enable_reg, , , JB4_q_a[13]_clock_0, JB4_q_a[13]_clock_1, JB4_q_a[13]_clock_enable_0, JB4_q_a[13]_clock_enable_1, , JB4_q_a[13]_clear_1);
JB4_q_a[13]_PORT_A_data_out_reg = DFFE(JB4_q_a[13]_PORT_A_data_out, JB4_q_a[13]_clock_0, JB4_q_a[13]_clear_1, , JB4_q_a[13]_clock_enable_0);
JB4_q_a[13] = JB4_q_a[13]_PORT_A_data_out_reg[0];


--JB3_q_a[13] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[13]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB3_q_a[13]_PORT_A_data_in = VCC;
JB3_q_a[13]_PORT_A_data_in_reg = DFFE(JB3_q_a[13]_PORT_A_data_in, JB3_q_a[13]_clock_0, , , JB3_q_a[13]_clock_enable_0);
JB3_q_a[13]_PORT_B_data_in = G1_mDATAOUT[13];
JB3_q_a[13]_PORT_B_data_in_reg = DFFE(JB3_q_a[13]_PORT_B_data_in, JB3_q_a[13]_clock_1, , , JB3_q_a[13]_clock_enable_1);
JB3_q_a[13]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[13]_PORT_A_address_reg = DFFE(JB3_q_a[13]_PORT_A_address, JB3_q_a[13]_clock_0, , , JB3_q_a[13]_clock_enable_0);
JB3_q_a[13]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[13]_PORT_B_address_reg = DFFE(JB3_q_a[13]_PORT_B_address, JB3_q_a[13]_clock_1, , , JB3_q_a[13]_clock_enable_1);
JB3_q_a[13]_PORT_A_write_enable = GND;
JB3_q_a[13]_PORT_A_write_enable_reg = DFFE(JB3_q_a[13]_PORT_A_write_enable, JB3_q_a[13]_clock_0, , , JB3_q_a[13]_clock_enable_0);
JB3_q_a[13]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[13]_PORT_B_write_enable_reg = DFFE(JB3_q_a[13]_PORT_B_write_enable, JB3_q_a[13]_clock_1, , , JB3_q_a[13]_clock_enable_1);
JB3_q_a[13]_clock_0 = CCD1_MCLK;
JB3_q_a[13]_clock_1 = MB1__clk0;
JB3_q_a[13]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[13]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[13]_clear_1 = !C1_oRST_0;
JB3_q_a[13]_PORT_A_data_out = MEMORY(JB3_q_a[13]_PORT_A_data_in_reg, JB3_q_a[13]_PORT_B_data_in_reg, JB3_q_a[13]_PORT_A_address_reg, JB3_q_a[13]_PORT_B_address_reg, JB3_q_a[13]_PORT_A_write_enable_reg, JB3_q_a[13]_PORT_B_write_enable_reg, , , JB3_q_a[13]_clock_0, JB3_q_a[13]_clock_1, JB3_q_a[13]_clock_enable_0, JB3_q_a[13]_clock_enable_1, , JB3_q_a[13]_clear_1);
JB3_q_a[13]_PORT_A_data_out_reg = DFFE(JB3_q_a[13]_PORT_A_data_out, JB3_q_a[13]_clock_0, JB3_q_a[13]_clear_1, , JB3_q_a[13]_clock_enable_0);
JB3_q_a[13] = JB3_q_a[13]_PORT_A_data_out_reg[0];


--B1L153 is VGA_Controller:u1|oVGA_R[8]~881
B1L153 = B1L156 & (A1L387 & JB4_q_a[13] # !A1L387 & (JB3_q_a[13]));


--JB4_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB4_q_a[14]_PORT_A_data_in = VCC;
JB4_q_a[14]_PORT_A_data_in_reg = DFFE(JB4_q_a[14]_PORT_A_data_in, JB4_q_a[14]_clock_0, , , JB4_q_a[14]_clock_enable_0);
JB4_q_a[14]_PORT_B_data_in = G1_mDATAOUT[14];
JB4_q_a[14]_PORT_B_data_in_reg = DFFE(JB4_q_a[14]_PORT_B_data_in, JB4_q_a[14]_clock_1, , , JB4_q_a[14]_clock_enable_1);
JB4_q_a[14]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[14]_PORT_A_address_reg = DFFE(JB4_q_a[14]_PORT_A_address, JB4_q_a[14]_clock_0, , , JB4_q_a[14]_clock_enable_0);
JB4_q_a[14]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[14]_PORT_B_address_reg = DFFE(JB4_q_a[14]_PORT_B_address, JB4_q_a[14]_clock_1, , , JB4_q_a[14]_clock_enable_1);
JB4_q_a[14]_PORT_A_write_enable = GND;
JB4_q_a[14]_PORT_A_write_enable_reg = DFFE(JB4_q_a[14]_PORT_A_write_enable, JB4_q_a[14]_clock_0, , , JB4_q_a[14]_clock_enable_0);
JB4_q_a[14]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[14]_PORT_B_write_enable_reg = DFFE(JB4_q_a[14]_PORT_B_write_enable, JB4_q_a[14]_clock_1, , , JB4_q_a[14]_clock_enable_1);
JB4_q_a[14]_clock_0 = CCD1_MCLK;
JB4_q_a[14]_clock_1 = MB1__clk0;
JB4_q_a[14]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[14]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[14]_clear_1 = !C1_oRST_0;
JB4_q_a[14]_PORT_A_data_out = MEMORY(JB4_q_a[14]_PORT_A_data_in_reg, JB4_q_a[14]_PORT_B_data_in_reg, JB4_q_a[14]_PORT_A_address_reg, JB4_q_a[14]_PORT_B_address_reg, JB4_q_a[14]_PORT_A_write_enable_reg, JB4_q_a[14]_PORT_B_write_enable_reg, , , JB4_q_a[14]_clock_0, JB4_q_a[14]_clock_1, JB4_q_a[14]_clock_enable_0, JB4_q_a[14]_clock_enable_1, , JB4_q_a[14]_clear_1);
JB4_q_a[14]_PORT_A_data_out_reg = DFFE(JB4_q_a[14]_PORT_A_data_out, JB4_q_a[14]_clock_0, JB4_q_a[14]_clear_1, , JB4_q_a[14]_clock_enable_0);
JB4_q_a[14] = JB4_q_a[14]_PORT_A_data_out_reg[0];


--JB3_q_a[14] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[14]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB3_q_a[14]_PORT_A_data_in = VCC;
JB3_q_a[14]_PORT_A_data_in_reg = DFFE(JB3_q_a[14]_PORT_A_data_in, JB3_q_a[14]_clock_0, , , JB3_q_a[14]_clock_enable_0);
JB3_q_a[14]_PORT_B_data_in = G1_mDATAOUT[14];
JB3_q_a[14]_PORT_B_data_in_reg = DFFE(JB3_q_a[14]_PORT_B_data_in, JB3_q_a[14]_clock_1, , , JB3_q_a[14]_clock_enable_1);
JB3_q_a[14]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[14]_PORT_A_address_reg = DFFE(JB3_q_a[14]_PORT_A_address, JB3_q_a[14]_clock_0, , , JB3_q_a[14]_clock_enable_0);
JB3_q_a[14]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[14]_PORT_B_address_reg = DFFE(JB3_q_a[14]_PORT_B_address, JB3_q_a[14]_clock_1, , , JB3_q_a[14]_clock_enable_1);
JB3_q_a[14]_PORT_A_write_enable = GND;
JB3_q_a[14]_PORT_A_write_enable_reg = DFFE(JB3_q_a[14]_PORT_A_write_enable, JB3_q_a[14]_clock_0, , , JB3_q_a[14]_clock_enable_0);
JB3_q_a[14]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[14]_PORT_B_write_enable_reg = DFFE(JB3_q_a[14]_PORT_B_write_enable, JB3_q_a[14]_clock_1, , , JB3_q_a[14]_clock_enable_1);
JB3_q_a[14]_clock_0 = CCD1_MCLK;
JB3_q_a[14]_clock_1 = MB1__clk0;
JB3_q_a[14]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[14]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[14]_clear_1 = !C1_oRST_0;
JB3_q_a[14]_PORT_A_data_out = MEMORY(JB3_q_a[14]_PORT_A_data_in_reg, JB3_q_a[14]_PORT_B_data_in_reg, JB3_q_a[14]_PORT_A_address_reg, JB3_q_a[14]_PORT_B_address_reg, JB3_q_a[14]_PORT_A_write_enable_reg, JB3_q_a[14]_PORT_B_write_enable_reg, , , JB3_q_a[14]_clock_0, JB3_q_a[14]_clock_1, JB3_q_a[14]_clock_enable_0, JB3_q_a[14]_clock_enable_1, , JB3_q_a[14]_clear_1);
JB3_q_a[14]_PORT_A_data_out_reg = DFFE(JB3_q_a[14]_PORT_A_data_out, JB3_q_a[14]_clock_0, JB3_q_a[14]_clear_1, , JB3_q_a[14]_clock_enable_0);
JB3_q_a[14] = JB3_q_a[14]_PORT_A_data_out_reg[0];


--B1L154 is VGA_Controller:u1|oVGA_R[9]~882
B1L154 = B1L156 & (A1L387 & JB4_q_a[14] # !A1L387 & (JB3_q_a[14]));


--JB4_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB4_q_a[5]_PORT_A_data_in = VCC;
JB4_q_a[5]_PORT_A_data_in_reg = DFFE(JB4_q_a[5]_PORT_A_data_in, JB4_q_a[5]_clock_0, , , JB4_q_a[5]_clock_enable_0);
JB4_q_a[5]_PORT_B_data_in = G1_mDATAOUT[5];
JB4_q_a[5]_PORT_B_data_in_reg = DFFE(JB4_q_a[5]_PORT_B_data_in, JB4_q_a[5]_clock_1, , , JB4_q_a[5]_clock_enable_1);
JB4_q_a[5]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[5]_PORT_A_address_reg = DFFE(JB4_q_a[5]_PORT_A_address, JB4_q_a[5]_clock_0, , , JB4_q_a[5]_clock_enable_0);
JB4_q_a[5]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[5]_PORT_B_address_reg = DFFE(JB4_q_a[5]_PORT_B_address, JB4_q_a[5]_clock_1, , , JB4_q_a[5]_clock_enable_1);
JB4_q_a[5]_PORT_A_write_enable = GND;
JB4_q_a[5]_PORT_A_write_enable_reg = DFFE(JB4_q_a[5]_PORT_A_write_enable, JB4_q_a[5]_clock_0, , , JB4_q_a[5]_clock_enable_0);
JB4_q_a[5]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[5]_PORT_B_write_enable_reg = DFFE(JB4_q_a[5]_PORT_B_write_enable, JB4_q_a[5]_clock_1, , , JB4_q_a[5]_clock_enable_1);
JB4_q_a[5]_clock_0 = CCD1_MCLK;
JB4_q_a[5]_clock_1 = MB1__clk0;
JB4_q_a[5]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[5]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[5]_clear_1 = !C1_oRST_0;
JB4_q_a[5]_PORT_A_data_out = MEMORY(JB4_q_a[5]_PORT_A_data_in_reg, JB4_q_a[5]_PORT_B_data_in_reg, JB4_q_a[5]_PORT_A_address_reg, JB4_q_a[5]_PORT_B_address_reg, JB4_q_a[5]_PORT_A_write_enable_reg, JB4_q_a[5]_PORT_B_write_enable_reg, , , JB4_q_a[5]_clock_0, JB4_q_a[5]_clock_1, JB4_q_a[5]_clock_enable_0, JB4_q_a[5]_clock_enable_1, , JB4_q_a[5]_clear_1);
JB4_q_a[5]_PORT_A_data_out_reg = DFFE(JB4_q_a[5]_PORT_A_data_out, JB4_q_a[5]_clock_0, JB4_q_a[5]_clear_1, , JB4_q_a[5]_clock_enable_0);
JB4_q_a[5] = JB4_q_a[5]_PORT_A_data_out_reg[0];


--JB3_q_a[5] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[5]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB3_q_a[5]_PORT_A_data_in = VCC;
JB3_q_a[5]_PORT_A_data_in_reg = DFFE(JB3_q_a[5]_PORT_A_data_in, JB3_q_a[5]_clock_0, , , JB3_q_a[5]_clock_enable_0);
JB3_q_a[5]_PORT_B_data_in = G1_mDATAOUT[5];
JB3_q_a[5]_PORT_B_data_in_reg = DFFE(JB3_q_a[5]_PORT_B_data_in, JB3_q_a[5]_clock_1, , , JB3_q_a[5]_clock_enable_1);
JB3_q_a[5]_PORT_A_address = BUS(BB3_power_modified_counter_values[0], BB3_power_modified_counter_values[1], BB3_power_modified_counter_values[2], BB3_power_modified_counter_values[3], BB3_power_modified_counter_values[4], BB3_power_modified_counter_values[5], BB3_power_modified_counter_values[6], BB3_power_modified_counter_values[7], BB3_power_modified_counter_values[8]);
JB3_q_a[5]_PORT_A_address_reg = DFFE(JB3_q_a[5]_PORT_A_address, JB3_q_a[5]_clock_0, , , JB3_q_a[5]_clock_enable_0);
JB3_q_a[5]_PORT_B_address = BUS(Z3_wrptr_g[0], Z3_wrptr_g[1], Z3_wrptr_g[2], Z3_wrptr_g[3], Z3_wrptr_g[4], Z3_wrptr_g[5], Z3_wrptr_g[6], Z3_wrptr_g[7], Z3_wrptr_g[8]);
JB3_q_a[5]_PORT_B_address_reg = DFFE(JB3_q_a[5]_PORT_B_address, JB3_q_a[5]_clock_1, , , JB3_q_a[5]_clock_enable_1);
JB3_q_a[5]_PORT_A_write_enable = GND;
JB3_q_a[5]_PORT_A_write_enable_reg = DFFE(JB3_q_a[5]_PORT_A_write_enable, JB3_q_a[5]_clock_0, , , JB3_q_a[5]_clock_enable_0);
JB3_q_a[5]_PORT_B_write_enable = Z3_valid_wrreq;
JB3_q_a[5]_PORT_B_write_enable_reg = DFFE(JB3_q_a[5]_PORT_B_write_enable, JB3_q_a[5]_clock_1, , , JB3_q_a[5]_clock_enable_1);
JB3_q_a[5]_clock_0 = CCD1_MCLK;
JB3_q_a[5]_clock_1 = MB1__clk0;
JB3_q_a[5]_clock_enable_0 = Z3_valid_rdreq;
JB3_q_a[5]_clock_enable_1 = Z3_valid_wrreq;
JB3_q_a[5]_clear_1 = !C1_oRST_0;
JB3_q_a[5]_PORT_A_data_out = MEMORY(JB3_q_a[5]_PORT_A_data_in_reg, JB3_q_a[5]_PORT_B_data_in_reg, JB3_q_a[5]_PORT_A_address_reg, JB3_q_a[5]_PORT_B_address_reg, JB3_q_a[5]_PORT_A_write_enable_reg, JB3_q_a[5]_PORT_B_write_enable_reg, , , JB3_q_a[5]_clock_0, JB3_q_a[5]_clock_1, JB3_q_a[5]_clock_enable_0, JB3_q_a[5]_clock_enable_1, , JB3_q_a[5]_clear_1);
JB3_q_a[5]_PORT_A_data_out_reg = DFFE(JB3_q_a[5]_PORT_A_data_out, JB3_q_a[5]_clock_0, JB3_q_a[5]_clear_1, , JB3_q_a[5]_clock_enable_0);
JB3_q_a[5] = JB3_q_a[5]_PORT_A_data_out_reg[0];


--B1L144 is VGA_Controller:u1|oVGA_G[5]~720
B1L144 = B1L156 & (A1L387 & JB4_q_a[5] # !A1L387 & (JB3_q_a[5]));


--JB4_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB4_q_a[6]_PORT_A_data_in = VCC;
JB4_q_a[6]_PORT_A_data_in_reg = DFFE(JB4_q_a[6]_PORT_A_data_in, JB4_q_a[6]_clock_0, , , JB4_q_a[6]_clock_enable_0);
JB4_q_a[6]_PORT_B_data_in = G1_mDATAOUT[6];
JB4_q_a[6]_PORT_B_data_in_reg = DFFE(JB4_q_a[6]_PORT_B_data_in, JB4_q_a[6]_clock_1, , , JB4_q_a[6]_clock_enable_1);
JB4_q_a[6]_PORT_A_address = BUS(BB4_power_modified_counter_values[0], BB4_power_modified_counter_values[1], BB4_power_modified_counter_values[2], BB4_power_modified_counter_values[3], BB4_power_modified_counter_values[4], BB4_power_modified_counter_values[5], BB4_power_modified_counter_values[6], BB4_power_modified_counter_values[7], BB4_power_modified_counter_values[8]);
JB4_q_a[6]_PORT_A_address_reg = DFFE(JB4_q_a[6]_PORT_A_address, JB4_q_a[6]_clock_0, , , JB4_q_a[6]_clock_enable_0);
JB4_q_a[6]_PORT_B_address = BUS(Z4_wrptr_g[0], Z4_wrptr_g[1], Z4_wrptr_g[2], Z4_wrptr_g[3], Z4_wrptr_g[4], Z4_wrptr_g[5], Z4_wrptr_g[6], Z4_wrptr_g[7], Z4_wrptr_g[8]);
JB4_q_a[6]_PORT_B_address_reg = DFFE(JB4_q_a[6]_PORT_B_address, JB4_q_a[6]_clock_1, , , JB4_q_a[6]_clock_enable_1);
JB4_q_a[6]_PORT_A_write_enable = GND;
JB4_q_a[6]_PORT_A_write_enable_reg = DFFE(JB4_q_a[6]_PORT_A_write_enable, JB4_q_a[6]_clock_0, , , JB4_q_a[6]_clock_enable_0);
JB4_q_a[6]_PORT_B_write_enable = Z4_valid_wrreq;
JB4_q_a[6]_PORT_B_write_enable_reg = DFFE(JB4_q_a[6]_PORT_B_write_enable, JB4_q_a[6]_clock_1, , , JB4_q_a[6]_clock_enable_1);
JB4_q_a[6]_clock_0 = CCD1_MCLK;
JB4_q_a[6]_clock_1 = MB1__clk0;
JB4_q_a[6]_clock_enable_0 = Z4_valid_rdreq;
JB4_q_a[6]_clock_enable_1 = Z4_valid_wrreq;
JB4_q_a[6]_clear_1 = !C1_oRST_0;
JB4_q_a[6]_PORT_A_data_out = MEMORY(JB4_q_a[6]_PORT_A_data_in_reg, JB4_q_a[6]_PORT_B_data_in_reg, JB4_q_a[6]_PORT_A_address_reg, JB4_q_a[6]_PORT_B_address_reg, JB4_q_a[6]_PORT_A_write_enable_reg, JB4_q_a[6]_PORT_B_write_enable_reg, , , JB4_q_a[6]_clock_0, JB4_q_a[6]_clock_1, JB4_q_a[6]_clock_enable_0, JB4_q_a[6]_clock_enable_1, , JB4_q_a[6]_clear_1);
JB4_q_a[6]_PORT_A_data_out_reg = DFFE(JB4_q_a[6]_PORT_A_data_out, JB4_q_a[6]_clock_0, JB4_q_a[6]_clear_1, , JB4_q_a[6]_clock_enable_0);
JB4_q_a[6] = JB4_q_a[6]_PORT_A_data_out_reg[0];


--JB3_q_a[6] is Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|altsyncram_61u:fifo_ram|altsyncram_rv91:altsyncram3|q_a[6]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 16, Port B Logical Depth: 512, Port B Logical Width: 16
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
JB3_q_a[6]_PORT_A_data_in = VCC;
JB3_q_a[6]_PORT_A_data_in_reg = DFFE(JB3_q_a[6]_PORT_A_data_in, JB3_q_a[6]_clock_0, , , JB3_q_a[6]_clock_enable_0);
JB3_q_a[6]_PORT_B_data_in = G1_mDATAOUT[6];
JB3_q_a[6]_PORT_B_data_in_reg = DFFE(JB3_q_a[6]_PORT_B_data