Fitter report for DE2_CCD_PIP
Tue Apr 04 19:16:00 2006
Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Netlist Optimizations
  6. Fitter Equations
  7. Pin-Out File
  8. Fitter Resource Usage Summary
  9. Input Pins
 10. Output Pins
 11. Bidir Pins
 12. I/O Bank Usage
 13. All Package Pins
 14. PLL Summary
 15. PLL Usage
 16. Clock Delay Control Summary
 17. Output Pin Default Load For Reported TCO
 18. Fitter Resource Utilization by Entity
 19. Delay Chain Summary
 20. Pad To Core Delay Chain Fanout
 21. Control Signals
 22. Global & Other Fast Signals
 23. Non-Global High Fan-Out Signals
 24. Fitter RAM Summary
 25. Interconnect Usage Summary
 26. LAB Logic Elements
 27. LAB-wide Signals
 28. LAB Signals Sourced
 29. LAB Signals Sourced Out
 30. LAB Distinct Inputs
 31. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



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; Fitter Summary                                                                     ;
+------------------------------------+-----------------------------------------------+
; Fitter Status                      ; Successful - Tue Apr 04 19:15:59 2006         ;
; Quartus II Version                 ; 5.1 Build 213 01/19/2006 SP 1 SJ Full Version ;
; Revision Name                      ; DE2_CCD_PIP                                   ;
; Top-level Entity Name              ; DE2_CCD_PIP                                   ;
; Family                             ; Cyclone II                                    ;
; Device                             ; EP2C35F672C6                                  ;
; Timing Models                      ; Preliminary                                   ;
; Total logic elements               ; 1,451 / 33,216 ( 4 % )                        ;
; Total registers                    ; 966                                           ;
; Total pins                         ; 425 / 475 ( 89 % )                            ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 97,264 / 483,840 ( 20 % )                     ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                                ;
; Total PLLs                         ; 1 / 4 ( 25 % )                                ;