?? clock.tan.qmsg
字號:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "counter6:u4\|c " "Info: Detected ripple clock \"counter6:u4\|c\" as buffer" { } { { "counter6.vhd" "" { Text "E:/CPLD/電子鐘/counter6.vhd" 10 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter6:u4\|c" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter10:u3\|c " "Info: Detected ripple clock \"counter10:u3\|c\" as buffer" { } { { "counter10.vhd" "" { Text "E:/CPLD/電子鐘/counter10.vhd" 10 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter10:u3\|c" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter6:u2\|c " "Info: Detected ripple clock \"counter6:u2\|c\" as buffer" { } { { "counter6.vhd" "" { Text "E:/CPLD/電子鐘/counter6.vhd" 10 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter6:u2\|c" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter10:u1\|c " "Info: Detected ripple clock \"counter10:u1\|c\" as buffer" { } { { "counter10.vhd" "" { Text "E:/CPLD/電子鐘/counter10.vhd" 10 -1 0 } } { "d:/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter10:u1\|c" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register counter24:u5\|count\[2\] register counter24:u5\|count\[5\] 185.74 MHz 5.384 ns Internal " "Info: Clock \"clk\" has Internal fmax of 185.74 MHz between source register \"counter24:u5\|count\[2\]\" and destination register \"counter24:u5\|count\[5\]\" (period= 5.384 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.675 ns + Longest register register " "Info: + Longest register to register delay is 4.675 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:u5\|count\[2\] 1 REG LC_X1_Y7_N9 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N9; Fanout = 11; REG Node = 'counter24:u5\|count\[2\]'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter24:u5|count[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.545 ns) + CELL(0.914 ns) 2.459 ns counter24:u5\|Equal0~36 2 COMB LC_X2_Y7_N8 2 " "Info: 2: + IC(1.545 ns) + CELL(0.914 ns) = 2.459 ns; Loc. = LC_X2_Y7_N8; Fanout = 2; COMB Node = 'counter24:u5\|Equal0~36'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.459 ns" { counter24:u5|count[2] counter24:u5|Equal0~36 } "NODE_NAME" } } { "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartus/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.155 ns) + CELL(1.061 ns) 4.675 ns counter24:u5\|count\[5\] 3 REG LC_X1_Y7_N1 5 " "Info: 3: + IC(1.155 ns) + CELL(1.061 ns) = 4.675 ns; Loc. = LC_X1_Y7_N1; Fanout = 5; REG Node = 'counter24:u5\|count\[5\]'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.216 ns" { counter24:u5|Equal0~36 counter24:u5|count[5] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.975 ns ( 42.25 % ) " "Info: Total cell delay = 1.975 ns ( 42.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 57.75 % ) " "Info: Total interconnect delay = 2.700 ns ( 57.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.675 ns" { counter24:u5|count[2] counter24:u5|Equal0~36 counter24:u5|count[5] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "4.675 ns" { counter24:u5|count[2] {} counter24:u5|Equal0~36 {} counter24:u5|count[5] {} } { 0.000ns 1.545ns 1.155ns } { 0.000ns 0.914ns 1.061ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 25.394 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 25.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 5 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 5; CLK Node = 'clk'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/CPLD/電子鐘/clock.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns counter10:u1\|c 2 REG LC_X10_Y8_N5 4 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y8_N5; Fanout = 4; REG Node = 'counter10:u1\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk counter10:u1|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/CPLD/電子鐘/counter10.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.052 ns) + CELL(1.294 ns) 10.541 ns counter6:u2\|c 3 REG LC_X8_Y8_N5 5 " "Info: 3: + IC(5.052 ns) + CELL(1.294 ns) = 10.541 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'counter6:u2\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.346 ns" { counter10:u1|c counter6:u2|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/CPLD/電子鐘/counter6.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.583 ns) + CELL(1.294 ns) 16.418 ns counter10:u3\|c 4 REG LC_X10_Y10_N7 4 " "Info: 4: + IC(4.583 ns) + CELL(1.294 ns) = 16.418 ns; Loc. = LC_X10_Y10_N7; Fanout = 4; REG Node = 'counter10:u3\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.877 ns" { counter6:u2|c counter10:u3|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/CPLD/電子鐘/counter10.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.029 ns) + CELL(1.294 ns) 19.741 ns counter6:u4\|c 5 REG LC_X11_Y8_N5 6 " "Info: 5: + IC(2.029 ns) + CELL(1.294 ns) = 19.741 ns; Loc. = LC_X11_Y8_N5; Fanout = 6; REG Node = 'counter6:u4\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { counter10:u3|c counter6:u4|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/CPLD/電子鐘/counter6.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.735 ns) + CELL(0.918 ns) 25.394 ns counter24:u5\|count\[5\] 6 REG LC_X1_Y7_N1 5 " "Info: 6: + IC(4.735 ns) + CELL(0.918 ns) = 25.394 ns; Loc. = LC_X1_Y7_N1; Fanout = 5; REG Node = 'counter24:u5\|count\[5\]'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.653 ns" { counter6:u4|c counter24:u5|count[5] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.257 ns ( 28.58 % ) " "Info: Total cell delay = 7.257 ns ( 28.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.137 ns ( 71.42 % ) " "Info: Total interconnect delay = 18.137 ns ( 71.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.394 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[5] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.394 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[5] {} } { 0.000ns 0.000ns 1.738ns 5.052ns 4.583ns 2.029ns 4.735ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 25.394 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 25.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 5 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 5; CLK Node = 'clk'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/CPLD/電子鐘/clock.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns counter10:u1\|c 2 REG LC_X10_Y8_N5 4 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y8_N5; Fanout = 4; REG Node = 'counter10:u1\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk counter10:u1|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/CPLD/電子鐘/counter10.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.052 ns) + CELL(1.294 ns) 10.541 ns counter6:u2\|c 3 REG LC_X8_Y8_N5 5 " "Info: 3: + IC(5.052 ns) + CELL(1.294 ns) = 10.541 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'counter6:u2\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.346 ns" { counter10:u1|c counter6:u2|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/CPLD/電子鐘/counter6.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.583 ns) + CELL(1.294 ns) 16.418 ns counter10:u3\|c 4 REG LC_X10_Y10_N7 4 " "Info: 4: + IC(4.583 ns) + CELL(1.294 ns) = 16.418 ns; Loc. = LC_X10_Y10_N7; Fanout = 4; REG Node = 'counter10:u3\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.877 ns" { counter6:u2|c counter10:u3|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/CPLD/電子鐘/counter10.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.029 ns) + CELL(1.294 ns) 19.741 ns counter6:u4\|c 5 REG LC_X11_Y8_N5 6 " "Info: 5: + IC(2.029 ns) + CELL(1.294 ns) = 19.741 ns; Loc. = LC_X11_Y8_N5; Fanout = 6; REG Node = 'counter6:u4\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { counter10:u3|c counter6:u4|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/CPLD/電子鐘/counter6.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.735 ns) + CELL(0.918 ns) 25.394 ns counter24:u5\|count\[2\] 6 REG LC_X1_Y7_N9 11 " "Info: 6: + IC(4.735 ns) + CELL(0.918 ns) = 25.394 ns; Loc. = LC_X1_Y7_N9; Fanout = 11; REG Node = 'counter24:u5\|count\[2\]'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.653 ns" { counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.257 ns ( 28.58 % ) " "Info: Total cell delay = 7.257 ns ( 28.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.137 ns ( 71.42 % ) " "Info: Total interconnect delay = 18.137 ns ( 71.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.394 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.394 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[2] {} } { 0.000ns 0.000ns 1.738ns 5.052ns 4.583ns 2.029ns 4.735ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.394 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[5] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.394 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[5] {} } { 0.000ns 0.000ns 1.738ns 5.052ns 4.583ns 2.029ns 4.735ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.394 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.394 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[2] {} } { 0.000ns 0.000ns 1.738ns 5.052ns 4.583ns 2.029ns 4.735ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.675 ns" { counter24:u5|count[2] counter24:u5|Equal0~36 counter24:u5|count[5] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "4.675 ns" { counter24:u5|count[2] {} counter24:u5|Equal0~36 {} counter24:u5|count[5] {} } { 0.000ns 1.545ns 1.155ns } { 0.000ns 0.914ns 1.061ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.394 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[5] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.394 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[5] {} } { 0.000ns 0.000ns 1.738ns 5.052ns 4.583ns 2.029ns 4.735ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.394 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.394 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[2] {} } { 0.000ns 0.000ns 1.738ns 5.052ns 4.583ns 2.029ns 4.735ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk hourh\[5\] counter24:u5\|count\[2\] 32.670 ns register " "Info: tco from clock \"clk\" to destination pin \"hourh\[5\]\" through register \"counter24:u5\|count\[2\]\" is 32.670 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 25.394 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 25.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 5 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 5; CLK Node = 'clk'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/CPLD/電子鐘/clock.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns counter10:u1\|c 2 REG LC_X10_Y8_N5 4 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y8_N5; Fanout = 4; REG Node = 'counter10:u1\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk counter10:u1|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/CPLD/電子鐘/counter10.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.052 ns) + CELL(1.294 ns) 10.541 ns counter6:u2\|c 3 REG LC_X8_Y8_N5 5 " "Info: 3: + IC(5.052 ns) + CELL(1.294 ns) = 10.541 ns; Loc. = LC_X8_Y8_N5; Fanout = 5; REG Node = 'counter6:u2\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.346 ns" { counter10:u1|c counter6:u2|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/CPLD/電子鐘/counter6.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.583 ns) + CELL(1.294 ns) 16.418 ns counter10:u3\|c 4 REG LC_X10_Y10_N7 4 " "Info: 4: + IC(4.583 ns) + CELL(1.294 ns) = 16.418 ns; Loc. = LC_X10_Y10_N7; Fanout = 4; REG Node = 'counter10:u3\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.877 ns" { counter6:u2|c counter10:u3|c } "NODE_NAME" } } { "counter10.vhd" "" { Text "E:/CPLD/電子鐘/counter10.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.029 ns) + CELL(1.294 ns) 19.741 ns counter6:u4\|c 5 REG LC_X11_Y8_N5 6 " "Info: 5: + IC(2.029 ns) + CELL(1.294 ns) = 19.741 ns; Loc. = LC_X11_Y8_N5; Fanout = 6; REG Node = 'counter6:u4\|c'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "3.323 ns" { counter10:u3|c counter6:u4|c } "NODE_NAME" } } { "counter6.vhd" "" { Text "E:/CPLD/電子鐘/counter6.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.735 ns) + CELL(0.918 ns) 25.394 ns counter24:u5\|count\[2\] 6 REG LC_X1_Y7_N9 11 " "Info: 6: + IC(4.735 ns) + CELL(0.918 ns) = 25.394 ns; Loc. = LC_X1_Y7_N9; Fanout = 11; REG Node = 'counter24:u5\|count\[2\]'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.653 ns" { counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.257 ns ( 28.58 % ) " "Info: Total cell delay = 7.257 ns ( 28.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.137 ns ( 71.42 % ) " "Info: Total interconnect delay = 18.137 ns ( 71.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.394 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.394 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[2] {} } { 0.000ns 0.000ns 1.738ns 5.052ns 4.583ns 2.029ns 4.735ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns + Longest register pin " "Info: + Longest register to pin delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter24:u5\|count\[2\] 1 REG LC_X1_Y7_N9 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N9; Fanout = 11; REG Node = 'counter24:u5\|count\[2\]'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter24:u5|count[2] } "NODE_NAME" } } { "counter24.vhd" "" { Text "E:/CPLD/電子鐘/counter24.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.561 ns) + CELL(0.914 ns) 2.475 ns decoder:u10\|Mux1~21 2 COMB LC_X2_Y7_N1 1 " "Info: 2: + IC(1.561 ns) + CELL(0.914 ns) = 2.475 ns; Loc. = LC_X2_Y7_N1; Fanout = 1; COMB Node = 'decoder:u10\|Mux1~21'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.475 ns" { counter24:u5|count[2] decoder:u10|Mux1~21 } "NODE_NAME" } } { "decoder.vhd" "" { Text "E:/CPLD/電子鐘/decoder.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.103 ns) + CELL(2.322 ns) 6.900 ns hourh\[5\] 3 PIN PIN_40 0 " "Info: 3: + IC(2.103 ns) + CELL(2.322 ns) = 6.900 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'hourh\[5\]'" { } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "4.425 ns" { decoder:u10|Mux1~21 hourh[5] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/CPLD/電子鐘/clock.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.236 ns ( 46.90 % ) " "Info: Total cell delay = 3.236 ns ( 46.90 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.664 ns ( 53.10 % ) " "Info: Total interconnect delay = 3.664 ns ( 53.10 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { counter24:u5|count[2] decoder:u10|Mux1~21 hourh[5] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { counter24:u5|count[2] {} decoder:u10|Mux1~21 {} hourh[5] {} } { 0.000ns 1.561ns 2.103ns } { 0.000ns 0.914ns 2.322ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} } { { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "25.394 ns" { clk counter10:u1|c counter6:u2|c counter10:u3|c counter6:u4|c counter24:u5|count[2] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "25.394 ns" { clk {} clk~combout {} counter10:u1|c {} counter6:u2|c {} counter10:u3|c {} counter6:u4|c {} counter24:u5|count[2] {} } { 0.000ns 0.000ns 1.738ns 5.052ns 4.583ns 2.029ns 4.735ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.900 ns" { counter24:u5|count[2] decoder:u10|Mux1~21 hourh[5] } "NODE_NAME" } } { "d:/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartus/quartus/bin/Technology_Viewer.qrui" "6.900 ns" { counter24:u5|count[2] {} decoder:u10|Mux1~21 {} hourh[5] {} } { 0.000ns 1.561ns 2.103ns } { 0.000ns 0.914ns 2.322ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Peak virtual memory: 124 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 19 22:38:17 2008 " "Info: Processing ended: Wed Nov 19 22:38:17 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
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