library ieee;
use ieee.std_logic_1164.all;

entity alaw_invert is
	port(
			data			:in			std_logic_vector(7 downto 0);	--pcm signal a
			ebi				:in			std_logic;						--enable even bit(a-law) inversion.1:inverted;0:not inverted
			dataq			:out		std_logic_vector(7 downto 0));	--output overlap signal
end alaw_invert;

architecture rtl of alaw_invert is
begin
	dataq <=  data(7) & (not data(6)) & data(5) & (not data(4)) & data(3) & (not data(2)) & data(1) & (not data(0))	when ebi = '1' else "ZZZZZZZZ"; 
    dataq <=  data when ebi = '0' else "ZZZZZZZZ";
--	dataq <=  data(7) & (not data(6)) & data(5) & (not data(4)) & data(3) & (not data(2)) & data(1) & (not data(0))	when ebi = '1' else  
--			  data ;
end rtl;