?? 65_conditioner_stim.vhd
字號:
--write by Diao Lan Song
--1998/9/24
LIBRARY IEEE;
Use IEEE.Std_Logic_1164.ALL;
ENTITY conditioner_stim IS END conditioner_stim ;
ARCHITECTURE stimulation OF conditioner_stim IS
COMPONENT conditioner
port(clk : IN Std_ULogic;
temp_high :IN Std_ULogic;
temp_low : IN Std_ULogic;
heat : OUT Std_ULogic;
cool : OUT Std_ULogic);
END COMPONENT;
SIGNAL clk : Std_ULogic;
SIGNAL temp_high : Std_ULogic;
SIGNAL temp_low : Std_ULogic;
SIGNAL heat : Std_ULogic;
SIGNAL cool : Std_ULogic;
BEGIN
comp1 : conditioner PORT MAP (clk,temp_high,temp_low,heat,cool);
conditioner_stim: PROCESS
BEGIN
temp_high <= '1';
temp_low <= '0';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '1';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '0';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '1';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '0';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '1';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '0';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '1';
WAIT UNTIL clk = '1';
temp_high <= '1';
temp_low <= '0';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '0';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '0';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '1';
WAIT UNTIL clk = '1';
temp_high <= '0';
temp_low <= '1';
WAIT UNTIL clk = '1';
ASSERT false REPORT "End of Simulation" SEVERITY error;
END PROCESS;
conditioner_clk: PROCESS
BEGIN
clk <= '1';
WHILE TRUE LOOP
clk <= '0';
WAIT FOR 50 ns;
clk <= '1';
WAIT FOR 50 ns;
END LOOP;
END PROCESS;
END stimulation;
configuration conditioner_stim_conf of conditioner_stim is
for stimulation
for comp1 : conditioner use entity work.air_conditioner(style_b);
end for;
end for;
end conditioner_stim_conf;
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