?? mul.fit.rpt
字號(hào):
; add~13 ; 1 ;
+-------------+-------------------+
+----------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; C4s ; 19 / 8,840 ( < 1 % ) ;
; Direct links ; 10 / 11,506 ( < 1 % ) ;
; Global clocks ; 0 / 8 ( 0 % ) ;
; LAB clocks ; 0 / 156 ( 0 % ) ;
; LUT chains ; 1 / 2,619 ( < 1 % ) ;
; Local interconnects ; 44 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 8 / 7,520 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 6.80) ; Number of LABs (Total = 5) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 3 ;
+--------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 6.80) ; Number of LABs (Total = 5) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 3 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 4.00) ; Number of LABs (Total = 5) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 7.20) ; Number of LABs (Total = 5) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 1 ;
; 12 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Wed Dec 17 13:04:36 2008
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off Mul -c Mul
Info: Selected device EP1C3T144C8 for design Mul
Info: Fitter is performing an Auto Fit compilation -- Fitter effort may be decreased to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C8 is compatible
Info: No exact pin location assignment(s) for 16 pins of 16 total pins
Info: Pin y[7] not assigned to an exact location on the device
Info: Pin y[6] not assigned to an exact location on the device
Info: Pin y[5] not assigned to an exact location on the device
Info: Pin y[4] not assigned to an exact location on the device
Info: Pin y[3] not assigned to an exact location on the device
Info: Pin y[2] not assigned to an exact location on the device
Info: Pin y[1] not assigned to an exact location on the device
Info: Pin y[0] not assigned to an exact location on the device
Info: Pin b[3] not assigned to an exact location on the device
Info: Pin b[2] not assigned to an exact location on the device
Info: Pin b[1] not assigned to an exact location on the device
Info: Pin b[0] not assigned to an exact location on the device
Info: Pin a[3] not assigned to an exact location on the device
Info: Pin a[2] not assigned to an exact location on the device
Info: Pin a[1] not assigned to an exact location on the device
Info: Pin a[0] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP scan-chain inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF, before I/O pin placement
Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 8 input, 8 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 18 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 24 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: Details of I/O bank after I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 10 total pin(s) used -- 10 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 8 total pin(s) used -- 16 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 28 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Dec 17 13:04:38 2008
Info: Elapsed time: 00:00:02
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