?? mul.map.rpt
字號:
Analysis & Synthesis report for Mul
Wed Dec 17 13:04:35 2008
Version 4.1 Build 181 06/29/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Multiplexer Restructuring Statistics (No Restructuring Performed)
5. WYSIWYG Cells
6. General Register Statistics
7. Hierarchy
8. Analysis & Synthesis Resource Utilization by Entity
9. Analysis & Synthesis Equations
10. Analysis & Synthesis Source Files Read
11. Analysis & Synthesis Resource Usage Summary
12. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Dec 17 13:04:35 2008 ;
; Quartus II Version ; 4.1 Build 181 06/29/2004 SJ Full Version ;
; Revision Name ; Mul ;
; Top-level Entity Name ; Mul ;
; Family ; Cyclone ;
; Total logic elements ; 34 ;
; Total pins ; 16 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device ; EP1C3T144C8 ; ;
; Family name ; Cyclone ; Stratix ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Top-level entity name ; Mul ; Mul ;
; State Machine Processing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- Cyclone ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+--------------------------------------------------------------------+--------------+---------------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (No Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |Mul|prod~15 ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |Mul|prod~12 ;
; 2:1 ; 2 bits ; 2 LEs ; 2 LEs ; 0 LEs ; No ; |Mul|prod~4 ;
; 2:1 ; 3 bits ; 3 LEs ; 3 LEs ; 0 LEs ; No ; |Mul|prod~8 ;
; 2:1 ; 4 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |Mul|prod~3 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 15 ;
; Number of synthesis-generated cells ; 19 ;
; Number of WYSIWYG LUTs ; 15 ;
; Number of synthesis-generated LUTs ; 19 ;
; Number of WYSIWYG registers ; 0 ;
; Number of synthesis-generated registers ; 0 ;
; Number of cells with combinational logic only ; 34 ;
; Number of cells with registers only ; 0 ;
; Number of cells with combinational logic and registers ; 0 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------+
; Hierarchy ;
+-----------+
Mul
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |Mul ; 34 (34) ; 0 ; 0 ; 16 ; 0 ; 34 (34) ; 0 (0) ; 0 (0) ; 15 (15) ; |Mul ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in d:/選做實驗2/mul/Mul.map.eqn.
+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-----------+----------------------------+
; File Name ; Used in Netlist ;
+-----------+----------------------------+
; Mul.vhd ; yes ;
+-----------+----------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 34 ;
; Total combinational functions ; 34 ;
; Total 4-input functions ; 6 ;
; Total 3-input functions ; 5 ;
; Total 2-input functions ; 19 ;
; Total 1-input functions ; 1 ;
; Total 0-input functions ; 3 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 0 ;
; Total logic cells in carry chains ; 15 ;
; I/O pins ; 16 ;
; Maximum fan-out node ; b[1] ;
; Maximum fan-out ; 7 ;
; Total fan-out ; 98 ;
; Average fan-out ; 1.96 ;
+-----------------------------------+---------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Wed Dec 17 13:04:34 2008
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Mul -c Mul
Info: Found 4 design units, including 1 entities, in source file Mul.vhd
Info: Found design unit 1: pack
Info: Found design unit 2: pack-body
Info: Found design unit 3: Mul-behave
Info: Found entity 1: Mul
Info: Implemented 50 device resources after synthesis - the final resource count might be different
Info: Implemented 8 input pins
Info: Implemented 8 output pins
Info: Implemented 34 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Wed Dec 17 13:04:35 2008
Info: Elapsed time: 00:00:00
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