<!--
This XML file (created on Tue Nov 11 23:07:10 2008) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_176.xsd</schema><license>
	<host_id>0000e8ef1a49</host_id>
	<nic_id>0000e8ef1a49</nic_id>
	<cdrive_id>ace49212</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>5.1</version>
	<build>Build 176</build>
	<binary_type>32</binary_type>
	<module>quartus_tan.exe</module>
	<edition>Full Version</edition>
	<compilation_end_time>Tue Nov 11 23:07:11 2008</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>1</proc_count>
		<cpu_freq units="MHz">868</cpu_freq>
	</cpu>
	<ram units="MB">256</ram>
</machine>
<top_file>D:/quartus/myproject/正弦信號發(fā)生器/sine</top_file>
<mep_data>
	<command_line>quartus_tan --read_settings_files=off --write_settings_files=off sine -c sine --timing_analysis_only</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
	<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning</info>
	<info>Info: Elapsed time: 00:00:11</info>
	<info>Info: Processing ended: Tue Nov 11 23:07:09 2008</info>
	<info>Info: th for register &quot;rom1:u1|altsyncram:altsyncram_component|altsyncram_4d51:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[3]&quot; (data pin = &quot;altera_internal_jtag&quot;, clock pin = &quot;altera_internal_jtag~TCKUTAP&quot;) is 0.273 ns</info>
	<info>Info: - Shortest pin to register delay is 3.658 ns</info>
</messages>
<clock_settings_summary>
	<row>
		<clock_node_name>clk</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
	<row>
		<clock_node_name>altera_internal_jtag~TCKUTAP</clock_node_name>
		<type>User Pin</type>
		<fmax_requirement>None</fmax_requirement>
		<early_latency units="ns">0.000</early_latency>
		<late_latency units="ns">0.000</late_latency>
		<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
		<divide_base_fmax_by>N/A</divide_base_fmax_by>
		<offset>N/A</offset>
	</row>
</clock_settings_summary>
<performance>
	<nonclk>
		<type>Worst-case tsu</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>2.919 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tco</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>8.983 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case tpd</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>3.026 ns</actual>
	</nonclk>
	<nonclk>
		<type>Worst-case th</type>
		<slack>N/A</slack>
		<required>None</required>
		<actual>0.273 ns</actual>
	</nonclk>
	<clk>
		<name>altera_internal_jtag~TCKUTAP</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>86.07 MHz ( period = 11.618 ns )</actual>
	</clk>
	<clk>
		<name>clk</name>
		<slack>N/A</slack>
		<required>None</required>
		<actual>Restricted to 163.03 MHz ( period = 6.134 ns )</actual>
	</clk>
</performance>
<compile_id>7A305C75</compile_id>
</talkback>