?? sine.vhd
字號(hào):
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sine is
port(
clk:in std_logic;
dout:out std_logic_vector(7 downto 0)
);
end entity sine;
architecture beh of sine is
component rom1
port(address:in std_logic_vector(5 downto 0);
clock:in std_logic;
q:out std_logic_vector(7 downto 0)
);
end component ;
signal q1:std_logic_vector(5 downto 0);
begin
process(clk)
begin
if clk 'event and clk='1' then
q1<=q1+1;
end if;
end process;
u1:rom1 port map(address=>q1,q=>dout,clock=>clk);
end architecture beh;
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