entity counter is
    Port ( F_CLKIN : in  STD_LOGIC;             --外部時鐘輸入
           TWE : in  STD_LOGIC;                 --外部數據總線賦值寫信號
           TD : in  STD_LOGIC_VECTOR (10 downto 0);  --外部總線
           CE : in  STD_LOGIC; 
			  RESET: in std_logic;
           CLK_INT : out  STD_LOGIC);            --分頻輸出
end counter;

architecture Behavioral of counter is
 
signal a:  std_logic_vector(10 downto 0);    
signal b:  std_logic_vector(10 downto 0);
signal c:  std_logic;
begin

  process(CE,TWE,F_CLKIN,TD,RESET)                    --分頻器進程  
      --采用時鐘同步寫信號， 
  begin
    if(RESET='0') then
	    a<="00000000000";
       b<="00000000000";
		 c<='0';
       CLK_INT<='0';
    else
    	 if (rising_edge(F_CLKIN)) then
	        if(CE='0' and TWE='0') then		   
               a<=TD;                          
	            b<=TD;
           		c<='1';	                      --c為標志位，c為1時才可以將clk int置1
	        elsif(a="00000000000" and c='1') then
      	  
               CLK_INT<='1';					   --CLK_INT 與lock 信號寬度為一個標頻周期
	            a<=b;
		     else
		         a<=a-1;
			      CLK_INT<='0';
	       end if; 
        end if; 
    end if;	 
  end process;

end Behavioral;