library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity  msecond is
port(
		clk, clr ,set       : in  std_logic;
		ensec             : out	std_logic;		
		daout             : out std_logic_vector (6 downto 0));
end entity  msecond;
architecture fun of  msecond is
signal count: std_logic_vector( 6 downto 0);
begin
daout <= count;
process ( clk,clr,set ) 
begin 
if (clr='1') then
count <="0000000";
elsif (set='0')then
  if (clk'event and clk='1') then
      if (count(3 downto 0)="1001") then
         if (count <"1100000") then
            if (count="1011001") then
                 count<="0000000";
                 ensec<='1';			          		           	   		
             else
                 count<=count+7; 
             end if;
           else 
            count<="0000000";
          end if;
       elsif(count <"1100000") then 
             count <= count + 1;
    		ensec<='0';
           else
             count<="0000000";
        end if;
  end if;
end if;
end process;
end fun;