library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity second is
port(
		clk, clr ,set    : in std_logic;
				 en:  in std_logic;
				set_clk: in  std_logic;
				set_min: in std_logic;
		enmin              : out std_logic;
        		  clkminout:  out std_logic_vector (6 downto 0);
		daout              : out std_logic_vector (6 downto 0));
end entity  second ;
architecture fun of  second is
signal count,clkmin: std_logic_vector( 6 downto 0);
signal clkin: std_logic;
begin

process(set_clk,clkmin,count)
begin
if(set_clk='1')then
  daout <= clkmin;
 clkminout<=clkmin;
else
  daout <= count;
end if;
end process;

process(clk,set_min,en)
begin
if(en='0')then
clkin<=clk;
else
clkin<=set_min;
end if;
end process;

process ( clkin,set_clk,set_min,clr,set ) 
begin 
if (clr='1') then
count <="0000000";
elsif (set='0')then
 if(set_clk='0')then
  if (clkin'event and clkin='1') then
      if (count(3 downto 0)="1001") then
         if (count <"1100000") then
            if (count="1011001") then
                 enmin <='1'; 
                 count<="0000000"; 				          		           	   		
             else
                 count<=count+7; 
             end if;
           else 
            count<="0000000";
          end if;
       elsif(count <"1100000") then 
             count <= count + 1;
             enmin <='0';
           else
             count<="0000000";
        end if;
  end if;
else
     if (set_min'event and set_min='1') then
      if (clkmin(3 downto 0)="1001") then
         if (clkmin <"1100000") then
            if (clkmin="1011001") then
                 clkmin<="0000000"; 				          		           	   		
             else
                 clkmin<=clkmin+7; 
             end if;
           else 
            clkmin <="0000000";
          end if;
       elsif(clkmin <"1100000") then 
             clkmin <= clkmin + 1;
           else
             clkmin<="0000000";
        end if;
  end if;
end if;
end if;
end process;
end fun;