?? watch.csf.qmsg
字號:
{ "Info" "ITAN_SCC_LOOP" "4 " "Info: Found combinational loop of 4 nodes" { { "Info" "ITAN_SCC_NODE" "act:u5\|daout1\[3\]~32 " "Info: Node act:u5\|daout1\[3\]~32" { } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 12 -1 0 } } } 0} { "Info" "ITAN_SCC_NODE" "act:u5\|i221~228 " "Info: Node act:u5\|i221~228" { } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 77 -1 0 } } } 0} { "Info" "ITAN_SCC_NODE" "act:u5\|i221~227 " "Info: Node act:u5\|i221~227" { } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 77 -1 0 } } } 0} { "Info" "ITAN_SCC_NODE" "act:u5\|i221~229 " "Info: Node act:u5\|i221~229" { } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 77 -1 0 } } } 0} } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 12 -1 0 } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 77 -1 0 } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 77 -1 0 } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 77 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "2 " "Info: Found combinational loop of 2 nodes" { { "Info" "ITAN_SCC_NODE" "act:u5\|i219~150 " "Info: Node act:u5\|i219~150" { } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 77 -1 0 } } } 0} { "Info" "ITAN_SCC_NODE" "act:u5\|daout1\[5\]~31 " "Info: Node act:u5\|daout1\[5\]~31" { } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 12 -1 0 } } } 0} } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 77 -1 0 } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 12 -1 0 } } } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 7 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node clk1 is an undefined clock" { } { { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 7 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "set_hour " "Info: Assuming node set_hour is an undefined clock" { } { { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 12 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "set_hour" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "en " "Info: Assuming node en is an undefined clock" { } { { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 10 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "en" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "set_min " "Info: Assuming node set_min is an undefined clock" { } { { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 13 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "set_min" } } } } } 0} } { } 0}
{ "Warning" "WTDB_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITDB_RIPPLE_CLK" "any_even:u1\|clk_outQ " "Info: Detected ripple clock any_even:u1\|clk_outQ as buffer" { } { { "e:/vdhl試驗/watch/any_even.vhd" "" "" { Text "e:/vdhl試驗/watch/any_even.vhd" 20 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "any_even:u1\|clk_outQ" } } } } } 0} { "Info" "ITDB_RIPPLE_CLK" "msecond:u2\|ensec~reg0 " "Info: Detected ripple clock msecond:u2\|ensec~reg0 as buffer" { } { { "e:/vdhl試驗/watch/msecond.vhd" "" "" { Text "e:/vdhl試驗/watch/msecond.vhd" 20 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "msecond:u2\|ensec~reg0" } } } } } 0} { "Info" "ITDB_GATED_CLK" "second:u3\|i33~3 " "Info: Detected gated clock second:u3\|i33~3 as buffer" { } { { "E:/vdhl試驗/watch/second.vhd" "" "" { Text "E:/vdhl試驗/watch/second.vhd" 32 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "second:u3\|i33~3" } } } } } 0} { "Info" "ITDB_RIPPLE_CLK" "second:u3\|enmin~reg0 " "Info: Detected ripple clock second:u3\|enmin~reg0 as buffer" { } { { "E:/vdhl試驗/watch/second.vhd" "" "" { Text "E:/vdhl試驗/watch/second.vhd" 45 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "second:u3\|enmin~reg0" } } } } } 0} { "Info" "ITDB_GATED_CLK" "minute:u4\|i15~3 " "Info: Detected gated clock minute:u4\|i15~3 as buffer" { } { { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 31 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "minute:u4\|i15~3" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register any_even:u1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] register any_even:u1\|clk_outQ 50.51 MHz 19.8 ns Internal " "Info: Clock clk has Internal fmax of 50.51 MHz between source register any_even:u1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] and destination register any_even:u1\|clk_outQ (period= 19.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.200 ns + Longest register register " "Info: + Longest register to register delay is 16.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns any_even:u1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 1 REG LC3_B4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B4; Fanout = 3; REG Node = 'any_even:u1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.700 ns) 3.900 ns any_even:u1\|i~329 2 COMB LC7_B3 1 " "Info: 2: + IC(2.200 ns) + CELL(1.700 ns) = 3.900 ns; Loc. = LC7_B3; Fanout = 1; COMB Node = 'any_even:u1\|i~329'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "3.900 ns" { any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[2] any_even:u1|i~329 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 5.400 ns any_even:u1\|i~332 3 COMB LC8_B3 1 " "Info: 3: + IC(0.000 ns) + CELL(1.500 ns) = 5.400 ns; Loc. = LC8_B3; Fanout = 1; COMB Node = 'any_even:u1\|i~332'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "1.500 ns" { any_even:u1|i~329 any_even:u1|i~332 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(2.300 ns) 10.000 ns any_even:u1\|i~1 4 COMB LC1_B9 26 " "Info: 4: + IC(2.300 ns) + CELL(2.300 ns) = 10.000 ns; Loc. = LC1_B9; Fanout = 26; COMB Node = 'any_even:u1\|i~1'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.600 ns" { any_even:u1|i~332 any_even:u1|i~1 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(1.800 ns) 14.400 ns any_even:u1\|clk_outQ~1 5 COMB LC1_B10 1 " "Info: 5: + IC(2.600 ns) + CELL(1.800 ns) = 14.400 ns; Loc. = LC1_B10; Fanout = 1; COMB Node = 'any_even:u1\|clk_outQ~1'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.400 ns" { any_even:u1|i~1 any_even:u1|clk_outQ~1 } "NODE_NAME" } } } { "e:/vdhl試驗/watch/any_even.vhd" "" "" { Text "e:/vdhl試驗/watch/any_even.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 16.200 ns any_even:u1\|clk_outQ 6 REG LC2_B10 9 " "Info: 6: + IC(0.600 ns) + CELL(1.200 ns) = 16.200 ns; Loc. = LC2_B10; Fanout = 9; REG Node = 'any_even:u1\|clk_outQ'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "1.800 ns" { any_even:u1|clk_outQ~1 any_even:u1|clk_outQ } "NODE_NAME" } } } { "e:/vdhl試驗/watch/any_even.vhd" "" "" { Text "e:/vdhl試驗/watch/any_even.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.500 ns 52.47 % " "Info: Total cell delay = 8.500 ns ( 52.47 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.700 ns 47.53 % " "Info: Total interconnect delay = 7.700 ns ( 47.53 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "16.200 ns" { any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[2] any_even:u1|i~329 any_even:u1|i~332 any_even:u1|i~1 any_even:u1|clk_outQ~1 any_even:u1|clk_outQ } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK Pin_1 26 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_1; Fanout = 26; CLK Node = 'clk'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns any_even:u1\|clk_outQ 2 REG LC2_B10 9 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_B10; Fanout = 9; REG Node = 'any_even:u1\|clk_outQ'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.500 ns" { clk any_even:u1|clk_outQ } "NODE_NAME" } } } { "e:/vdhl試驗/watch/any_even.vhd" "" "" { Text "e:/vdhl試驗/watch/any_even.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk any_even:u1|clk_outQ } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK Pin_1 26 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_1; Fanout = 26; CLK Node = 'clk'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns any_even:u1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\] 2 REG LC3_B4 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_B4; Fanout = 3; REG Node = 'any_even:u1\|lpm_counter:coutQ_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[2\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.500 ns" { clk any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } } { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } } } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk any_even:u1|clk_outQ } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" "" "" { Text "c:/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 277 2 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "e:/vdhl試驗/watch/any_even.vhd" "" "" { Text "e:/vdhl試驗/watch/any_even.vhd" 20 -1 0 } } } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "16.200 ns" { any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[2] any_even:u1|i~329 any_even:u1|i~332 any_even:u1|i~1 any_even:u1|clk_outQ~1 any_even:u1|clk_outQ } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk any_even:u1|clk_outQ } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk any_even:u1|lpm_counter:coutQ_rtl_0|alt_counter_f10ke:wysi_counter|q[2] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register act:u5\|count\[1\] register act:u5\|num\[1\] 46.73 MHz 21.4 ns Internal " "Info: Clock clk1 has Internal fmax of 46.73 MHz between source register act:u5\|count\[1\] and destination register act:u5\|num\[1\] (period= 21.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.800 ns + Longest register register " "Info: + Longest register to register delay is 17.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns act:u5\|count\[1\] 1 REG LC2_C19 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C19; Fanout = 16; REG Node = 'act:u5\|count\[1\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { act:u5|count[1] } "NODE_NAME" } } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(2.300 ns) 5.000 ns act:u5\|i102~84 2 COMB LC4_C13 2 " "Info: 2: + IC(2.700 ns) + CELL(2.300 ns) = 5.000 ns; Loc. = LC4_C13; Fanout = 2; COMB Node = 'act:u5\|i102~84'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.000 ns" { act:u5|count[1] act:u5|i102~84 } "NODE_NAME" } } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 7.900 ns act:u5\|i82~555 3 COMB LC6_C13 3 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 7.900 ns; Loc. = LC6_C13; Fanout = 3; COMB Node = 'act:u5\|i82~555'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.900 ns" { act:u5|i102~84 act:u5|i82~555 } "NODE_NAME" } } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 51 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(2.300 ns) 12.600 ns act:u5\|i83~532 4 COMB LC6_C16 1 " "Info: 4: + IC(2.400 ns) + CELL(2.300 ns) = 12.600 ns; Loc. = LC6_C16; Fanout = 1; COMB Node = 'act:u5\|i83~532'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.700 ns" { act:u5|i82~555 act:u5|i83~532 } "NODE_NAME" } } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 51 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 15.500 ns act:u5\|i83~538 5 COMB LC4_C16 1 " "Info: 5: + IC(0.600 ns) + CELL(2.300 ns) = 15.500 ns; Loc. = LC4_C16; Fanout = 1; COMB Node = 'act:u5\|i83~538'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.900 ns" { act:u5|i83~532 act:u5|i83~538 } "NODE_NAME" } } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 51 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 17.800 ns act:u5\|num\[1\] 6 REG LC1_C16 15 " "Info: 6: + IC(0.600 ns) + CELL(1.700 ns) = 17.800 ns; Loc. = LC1_C16; Fanout = 15; REG Node = 'act:u5\|num\[1\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.300 ns" { act:u5|i83~538 act:u5|num[1] } "NODE_NAME" } } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.900 ns 61.24 % " "Info: Total cell delay = 10.900 ns ( 61.24 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns 38.76 % " "Info: Total interconnect delay = 6.900 ns ( 38.76 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "17.800 ns" { act:u5|count[1] act:u5|i102~84 act:u5|i82~555 act:u5|i83~532 act:u5|i83~538 act:u5|num[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock clk1 to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk1 1 CLK Pin_2 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_2; Fanout = 14; CLK Node = 'clk1'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { clk1 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns act:u5\|num\[1\] 2 REG LC1_C16 15 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C16; Fanout = 15; REG Node = 'act:u5\|num\[1\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.500 ns" { clk1 act:u5|num[1] } "NODE_NAME" } } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u5|num[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 5.300 ns - Longest register " "Info: - Longest clock path from clock clk1 to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk1 1 CLK Pin_2 14 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_2; Fanout = 14; CLK Node = 'clk1'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { clk1 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns act:u5\|count\[1\] 2 REG LC2_C19 16 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC2_C19; Fanout = 16; REG Node = 'act:u5\|count\[1\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.500 ns" { clk1 act:u5|count[1] } "NODE_NAME" } } } { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u5|count[1] } "NODE_NAME" } } } } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u5|num[1] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u5|count[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 26 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "e:/vdhl試驗/watch/act.vhd" "" "" { Text "e:/vdhl試驗/watch/act.vhd" 26 -1 0 } } } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "17.800 ns" { act:u5|count[1] act:u5|i102~84 act:u5|i82~555 act:u5|i83~532 act:u5|i83~538 act:u5|num[1] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u5|num[1] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { clk1 act:u5|count[1] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "set_hour register minute:u4\|count\[3\] register minute:u4\|clkhour\[6\] 40.32 MHz 24.8 ns Internal " "Info: Clock set_hour has Internal fmax of 40.32 MHz between source register minute:u4\|count\[3\] and destination register minute:u4\|clkhour\[6\] (period= 24.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.000 ns + Longest register register " "Info: + Longest register to register delay is 17.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute:u4\|count\[3\] 1 REG LC6_A3 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A3; Fanout = 7; REG Node = 'minute:u4\|count\[3\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { minute:u4|count[3] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns minute:u4\|i~309 2 COMB LC8_A3 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC8_A3; Fanout = 1; COMB Node = 'minute:u4\|i~309'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.900 ns" { minute:u4|count[3] minute:u4|i~309 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 5.300 ns minute:u4\|i~310 3 COMB LC2_A3 1 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 5.300 ns; Loc. = LC2_A3; Fanout = 1; COMB Node = 'minute:u4\|i~310'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.400 ns" { minute:u4|i~309 minute:u4|i~310 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 9.800 ns minute:u4\|i~311 4 COMB LC1_A2 9 " "Info: 4: + IC(2.200 ns) + CELL(2.300 ns) = 9.800 ns; Loc. = LC1_A2; Fanout = 9; COMB Node = 'minute:u4\|i~311'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.500 ns" { minute:u4|i~310 minute:u4|i~311 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.300 ns) 14.700 ns minute:u4\|i139~274 5 COMB LC3_A1 3 " "Info: 5: + IC(2.600 ns) + CELL(2.300 ns) = 14.700 ns; Loc. = LC3_A1; Fanout = 3; COMB Node = 'minute:u4\|i139~274'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.900 ns" { minute:u4|i~311 minute:u4|i139~274 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 73 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 17.000 ns minute:u4\|clkhour\[6\] 6 REG LC6_A1 6 " "Info: 6: + IC(0.600 ns) + CELL(1.700 ns) = 17.000 ns; Loc. = LC6_A1; Fanout = 6; REG Node = 'minute:u4\|clkhour\[6\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.300 ns" { minute:u4|i139~274 minute:u4|clkhour[6] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 72 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.400 ns 61.18 % " "Info: Total cell delay = 10.400 ns ( 61.18 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns 38.82 % " "Info: Total interconnect delay = 6.600 ns ( 38.82 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "17.000 ns" { minute:u4|count[3] minute:u4|i~309 minute:u4|i~310 minute:u4|i~311 minute:u4|i139~274 minute:u4|clkhour[6] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.200 ns - Smallest " "Info: - Smallest clock skew is -4.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "set_hour destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock set_hour to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns set_hour 1 CLK Pin_44 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_44; Fanout = 8; CLK Node = 'set_hour'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { set_hour } "NODE_NAME" } } } { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns minute:u4\|clkhour\[6\] 2 REG LC6_A1 6 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_A1; Fanout = 6; REG Node = 'minute:u4\|clkhour\[6\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.500 ns" { set_hour minute:u4|clkhour[6] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 72 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { set_hour minute:u4|clkhour[6] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "set_hour source 9.500 ns - Longest register " "Info: - Longest clock path from clock set_hour to source register is 9.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns set_hour 1 CLK Pin_44 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_44; Fanout = 8; CLK Node = 'set_hour'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { set_hour } "NODE_NAME" } } } { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.800 ns) 6.200 ns minute:u4\|i15~3 2 COMB LC4_A17 7 " "Info: 2: + IC(1.600 ns) + CELL(1.800 ns) = 6.200 ns; Loc. = LC4_A17; Fanout = 7; COMB Node = 'minute:u4\|i15~3'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "3.400 ns" { set_hour minute:u4|i15~3 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 9.500 ns minute:u4\|count\[3\] 3 REG LC6_A3 7 " "Info: 3: + IC(3.300 ns) + CELL(0.000 ns) = 9.500 ns; Loc. = LC6_A3; Fanout = 7; REG Node = 'minute:u4\|count\[3\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "3.300 ns" { minute:u4|i15~3 minute:u4|count[3] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns 48.42 % " "Info: Total cell delay = 4.600 ns ( 48.42 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns 51.58 % " "Info: Total interconnect delay = 4.900 ns ( 51.58 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "9.500 ns" { set_hour minute:u4|i15~3 minute:u4|count[3] } "NODE_NAME" } } } } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { set_hour minute:u4|clkhour[6] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "9.500 ns" { set_hour minute:u4|i15~3 minute:u4|count[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 72 -1 0 } } } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "17.000 ns" { minute:u4|count[3] minute:u4|i~309 minute:u4|i~310 minute:u4|i~311 minute:u4|i139~274 minute:u4|clkhour[6] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.300 ns" { set_hour minute:u4|clkhour[6] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "9.500 ns" { set_hour minute:u4|i15~3 minute:u4|count[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "en register minute:u4\|count\[3\] register minute:u4\|count\[6\] 38.02 MHz 26.3 ns Internal " "Info: Clock en has Internal fmax of 38.02 MHz between source register minute:u4\|count\[3\] and destination register minute:u4\|count\[6\] (period= 26.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.300 ns + Longest register register " "Info: + Longest register to register delay is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute:u4\|count\[3\] 1 REG LC6_A3 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_A3; Fanout = 7; REG Node = 'minute:u4\|count\[3\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { minute:u4|count[3] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 2.900 ns minute:u4\|i~309 2 COMB LC8_A3 1 " "Info: 2: + IC(0.600 ns) + CELL(2.300 ns) = 2.900 ns; Loc. = LC8_A3; Fanout = 1; COMB Node = 'minute:u4\|i~309'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.900 ns" { minute:u4|count[3] minute:u4|i~309 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.800 ns) 5.300 ns minute:u4\|i~310 3 COMB LC2_A3 1 " "Info: 3: + IC(0.600 ns) + CELL(1.800 ns) = 5.300 ns; Loc. = LC2_A3; Fanout = 1; COMB Node = 'minute:u4\|i~310'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.400 ns" { minute:u4|i~309 minute:u4|i~310 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 9.800 ns minute:u4\|i~311 4 COMB LC1_A2 9 " "Info: 4: + IC(2.200 ns) + CELL(2.300 ns) = 9.800 ns; Loc. = LC1_A2; Fanout = 9; COMB Node = 'minute:u4\|i~311'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.500 ns" { minute:u4|i~310 minute:u4|i~311 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(1.700 ns) 14.300 ns minute:u4\|count\[6\] 5 REG LC1_A6 6 " "Info: 5: + IC(2.800 ns) + CELL(1.700 ns) = 14.300 ns; Loc. = LC1_A6; Fanout = 6; REG Node = 'minute:u4\|count\[6\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.500 ns" { minute:u4|i~311 minute:u4|count[6] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns 56.64 % " "Info: Total cell delay = 8.100 ns ( 56.64 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.200 ns 43.36 % " "Info: Total interconnect delay = 6.200 ns ( 43.36 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "14.300 ns" { minute:u4|count[3] minute:u4|i~309 minute:u4|i~310 minute:u4|i~311 minute:u4|count[6] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.400 ns - Smallest " "Info: - Smallest clock skew is -8.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "en destination 12.700 ns + Shortest register " "Info: + Shortest clock path from clock en to destination register is 12.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns en 1 CLK Pin_6 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = Pin_6; Fanout = 2; CLK Node = 'en'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { en } "NODE_NAME" } } } { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(2.300 ns) 9.500 ns minute:u4\|i15~3 2 COMB LC4_A17 7 " "Info: 2: + IC(3.700 ns) + CELL(2.300 ns) = 9.500 ns; Loc. = LC4_A17; Fanout = 7; COMB Node = 'minute:u4\|i15~3'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "6.000 ns" { en minute:u4|i15~3 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(0.000 ns) 12.700 ns minute:u4\|count\[6\] 3 REG LC1_A6 6 " "Info: 3: + IC(3.200 ns) + CELL(0.000 ns) = 12.700 ns; Loc. = LC1_A6; Fanout = 6; REG Node = 'minute:u4\|count\[6\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "3.200 ns" { minute:u4|i15~3 minute:u4|count[6] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 45.67 % " "Info: Total cell delay = 5.800 ns ( 45.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns 54.33 % " "Info: Total interconnect delay = 6.900 ns ( 54.33 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "12.700 ns" { en minute:u4|i15~3 minute:u4|count[6] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "en source 21.100 ns - Longest register " "Info: - Longest clock path from clock en to source register is 21.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns en 1 CLK Pin_6 2 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = Pin_6; Fanout = 2; CLK Node = 'en'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { en } "NODE_NAME" } } } { "E:/vdhl試驗/watch/watch.vhd" "" "" { Text "E:/vdhl試驗/watch/watch.vhd" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(2.300 ns) 9.300 ns second:u3\|i33~3 2 COMB LC1_C7 8 " "Info: 2: + IC(3.500 ns) + CELL(2.300 ns) = 9.300 ns; Loc. = LC1_C7; Fanout = 8; COMB Node = 'second:u3\|i33~3'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.800 ns" { en second:u3|i33~3 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/second.vhd" "" "" { Text "E:/vdhl試驗/watch/second.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(1.100 ns) 14.900 ns second:u3\|enmin~reg0 3 REG LC3_A17 2 " "Info: 3: + IC(4.500 ns) + CELL(1.100 ns) = 14.900 ns; Loc. = LC3_A17; Fanout = 2; REG Node = 'second:u3\|enmin~reg0'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "5.600 ns" { second:u3|i33~3 second:u3|enmin~reg0 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/second.vhd" "" "" { Text "E:/vdhl試驗/watch/second.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 17.800 ns minute:u4\|i15~3 4 COMB LC4_A17 7 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 17.800 ns; Loc. = LC4_A17; Fanout = 7; COMB Node = 'minute:u4\|i15~3'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "2.900 ns" { second:u3|enmin~reg0 minute:u4|i15~3 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.000 ns) 21.100 ns minute:u4\|count\[3\] 5 REG LC6_A3 7 " "Info: 5: + IC(3.300 ns) + CELL(0.000 ns) = 21.100 ns; Loc. = LC6_A3; Fanout = 7; REG Node = 'minute:u4\|count\[3\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "3.300 ns" { minute:u4|i15~3 minute:u4|count[3] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.200 ns 43.60 % " "Info: Total cell delay = 9.200 ns ( 43.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.900 ns 56.40 % " "Info: Total interconnect delay = 11.900 ns ( 56.40 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "21.100 ns" { en second:u3|i33~3 second:u3|enmin~reg0 minute:u4|i15~3 minute:u4|count[3] } "NODE_NAME" } } } } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "12.700 ns" { en minute:u4|i15~3 minute:u4|count[6] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "21.100 ns" { en second:u3|i33~3 second:u3|enmin~reg0 minute:u4|i15~3 minute:u4|count[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "E:/vdhl試驗/watch/minute.vhd" "" "" { Text "E:/vdhl試驗/watch/minute.vhd" 54 -1 0 } } } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "14.300 ns" { minute:u4|count[3] minute:u4|i~309 minute:u4|i~310 minute:u4|i~311 minute:u4|count[6] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "12.700 ns" { en minute:u4|i15~3 minute:u4|count[6] } "NODE_NAME" } } } { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "21.100 ns" { en second:u3|i33~3 second:u3|enmin~reg0 minute:u4|i15~3 minute:u4|count[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "set_min register second:u3\|count\[2\] register second:u3\|count\[4\] 51.55 MHz 19.4 ns Internal " "Info: Clock set_min has Internal fmax of 51.55 MHz between source register second:u3\|count\[2\] and destination register second:u3\|count\[4\] (period= 19.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.800 ns + Longest register register " "Info: + Longest register to register delay is 15.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns second:u3\|count\[2\] 1 REG LC8_A19 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A19; Fanout = 5; REG Node = 'second:u3\|count\[2\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "" { second:u3|count[2] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/second.vhd" "" "" { Text "E:/vdhl試驗/watch/second.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(2.300 ns) 4.700 ns second:u3\|i~153 2 COMB LC1_A18 3 " "Info: 2: + IC(2.400 ns) + CELL(2.300 ns) = 4.700 ns; Loc. = LC1_A18; Fanout = 3; COMB Node = 'second:u3\|i~153'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.700 ns" { second:u3|count[2] second:u3|i~153 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.300 ns) 9.100 ns second:u3\|i80~42 3 COMB LC2_A17 8 " "Info: 3: + IC(2.100 ns) + CELL(2.300 ns) = 9.100 ns; Loc. = LC2_A17; Fanout = 8; COMB Node = 'second:u3\|i80~42'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.400 ns" { second:u3|i~153 second:u3|i80~42 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/second.vhd" "" "" { Text "E:/vdhl試驗/watch/second.vhd" 46 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.300 ns) 14.000 ns second:u3\|i76~98 4 COMB LC8_A13 1 " "Info: 4: + IC(2.600 ns) + CELL(2.300 ns) = 14.000 ns; Loc. = LC8_A13; Fanout = 1; COMB Node = 'second:u3\|i76~98'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "4.900 ns" { second:u3|i80~42 second:u3|i76~98 } "NODE_NAME" } } } { "E:/vdhl試驗/watch/second.vhd" "" "" { Text "E:/vdhl試驗/watch/second.vhd" 46 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 15.800 ns second:u3\|count\[4\] 5 REG LC1_A13 7 " "Info: 5: + IC(0.600 ns) + CELL(1.200 ns) = 15.800 ns; Loc. = LC1_A13; Fanout = 7; REG Node = 'second:u3\|count\[4\]'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "1.800 ns" { second:u3|i76~98 second:u3|count[4] } "NODE_NAME" } } } { "E:/vdhl試驗/watch/second.vhd" "" "" { Text "E:/vdhl試驗/watch/second.vhd" 45 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.100 ns 51.27 % " "Info: Total cell delay = 8.100 ns ( 51.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.700 ns 48.73 % " "Info: Total interconnect delay = 7.700 ns ( 48.73 % )" { } { } 0} } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "" "" "15.800 ns" { second:u3|count[2] second:u3|i~153 second:u3|i80~42 second:u3|i76~98 second:u3|count[4] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "set_min destination 10.700 ns + Shortest register " "Info: + Shortest clock path from clock set_min to destination register is 10.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns set_min 1 CLK Pin_84 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = Pin_84; Fanout = 8; CLK Node = 'set_min'" { } { { "E:/王明/shiyan10/db/watch_cmp.qrpt" "" "" { Report "E:/王明/shiyan10/db/watch_cmp.qrpt" Compiler "watch" "UNKNOWN" "V1" "E:/王明/shiyan10/db/watch.quartus_db" { Floorplan "?? 快捷鍵說明
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