library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity  minute is
port(
		clk, clr ,set       : in  std_logic;
		      en:  in std_logic;
		set_clk:  in std_logic;
         set_hour: in std_logic;
         set_fun:  in std_logic;
      clkhourout:  out std_logic_vector (6 downto 0);
		daout    : out std_logic_vector (6 downto 0));
end entity  minute;
architecture fun of  minute is
signal count,clkhour,hourset: std_logic_vector( 6 downto 0);
signal clkin: std_logic;
begin

process(set_fun)
begin
if(set_fun='1')then
hourset<="0010001";
else
hourset<="0100011";
end if;
end process;

process(clk,set_hour,en)
begin
if(en='0')then
clkin<=clk;
else
clkin<=set_hour;
end if;
end process;

process(set_clk,clkhour,count)
begin
if(set_clk='1')then
  daout<=clkhour;
   clkhourout<=clkhour;
else
  daout <= count;
end if;
end process;

process ( clkin,clr,set ) 
begin 
if (clr='1') then
count <="0000000";
elsif (set='0')then
    if(set_clk='0')then
     if (clkin'event and clkin='1') then
      if (count(3 downto 0)="1001") then
         if (count <hourset) then
            if (count=hourset) then
                 count<="0000000"; 			
             else
                 count<=count+7; 
             end if;
           else 
            count<="0000000";
          end if;
       elsif(count <hourset) then 
             count <= count + 1;
           else
             count<="0000000";
        end if;
     end if;
   else
         if (set_hour'event and set_hour='1') then
      if (clkhour(3 downto 0)="1001") then
         if (clkhour <hourset) then
            if (clkhour=hourset) then
                 clkhour<="0000000"; 			
             else
                 clkhour<=clkhour+7; 
             end if;
           else 
            clkhour<="0000000";
          end if;
       elsif(count <hourset) then 
             clkhour <= clkhour + 1;
           else
             clkhour<="0000000";
        end if;
     end if;
end if;
end if;
end process;
end fun;