/****************************************************************************************************   Copyright(c) Hynix Semiconductor Inc., 2003. All rights reserved.   File Name   :  SDR.v   Part Number :  SDR SDRAM   Description :  Verilog-HDL Model of Hynix Semiconductor SDR SDRAM   Version     :  Rev0.0   Date        :  Dec.22, 2003   Model       :  BUS Functional   Author      :  Beom-ju Shin   Verilog-XL  :  Version 3.4                  verilog +define+DEVICE_TYPE+SPEC test_SDR.v SDR.v   VCS         :  Version 6.0                  vcs -R +define+DEVICE_TYPE+SPEC test_SDR.v SDR.v                  DEVICE            DEVICE_TYPE                   64Mb SDRAM(X4)   SDR64Mx4                   64Mb SDRAM(X8)   SDR64Mx8                   64Mb SDRAM(X16)  SDR64Mx16                  128Mb SDRAM(X4)   SDR128Mx4                  128Mb SDRAM(X8)   SDR128Mx8                  128Mb SDRAM(X16)  SDR128Mx16                  SPEC : SDR_6, SDR_K, SDR_H, SDR_8, SDR_P, SDR_S   Notice      :  You must define clock cycle time in test bench file as following;                  `define  tCK  6   Rev0.1      :  ****************************************************************************************************//************************   AC CHARACTERISTICS************************/`ifdef SDR_6   `define  tCK3min         6  // system clock cycle time(CL=3)[ns]   `define  tCK3max      1000  // system clock cycle time(CL=3)[ns]   `define  tCK2min        10  // system clock cycle time(CL=2)[ns]   `define  tCK2max      1000  // system clock cycle time(CL=2)[ns]   `define  tCHWmin       2.5  // clock high pulse width[ns]   `define  tCLWmin       2.5  // clock low pulse width[ns]   `define  tAC3max       5.4  // access time from clock(CL=3)[ns]   `define  tAC2max         6  // access time from clock(CL=2)[ns]   `define  tOHmin        2.7  // data-out hold time[ns]   `define  tDSmin        1.5  // data-input setup time[ns]   `define  tDHmin        0.8  // data-input hold time[ns]   `define  tASmin        1.5  // address setup time[ns]   `define  tAHmin        0.8  // address hold time[ns]   `define  tCKSmin       1.5  // CKE setup time[ns]   `define  tCKHmin       0.8  // CKE hold time[ns]   `define  tCSmin        1.5  // command setup time[ns]   `define  tCHmin        0.8  // command hold time[ns]   `define  tOLZmin         1  // clock to data output in Low-Z time[ns]   `define  tOHZ3min      2.7  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ3max      5.4  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ2min      2.7  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tOHZ2max      5.4  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tRCmin         60  // RAS cycle time @ operation[ns]   `define  tRFCmin        60  // RAS cycle time @ auto refresh[ns]   `define  tRCDmin        18  // RAS to CAS delay[ns]   `define  tRASmin        42  // RAS active time[ns]   `define  tRASmax    100000  // RAS active time[ns]   `define  tRPmin         18  // RAS precharge time[ns]   `define  tRRDmin        12  // RAS to RAS bank active delay[ns]   `define  tCCDmin         1  // CAS to CAS delay[tCK]   `define  tWTLmin         0  // write command to data-in delay[tCK]   `define  tDPLmin         2  // data-in to precharge delay[tCK]   `define  tDALmin         5  // data-in to active command[tCK]   `define  tDQZmin         2  // DQM to data-out Hi-Z[tCK]   `define  tDQMmin         0  // DQM to data-in mask[tCK]   `define  tMRDmin         2  // MRS to new command[tCK]   `define  tPROZ3min       3  // precharge to data output Hi-Z(CL=3)[tCK]   `define  tPROZ2min       2  // precharge to data output Hi-Z(CL=2)[tCK]   `define  tPDEmin         1  // power down exit time[tCK]   `define  tSREmin         1  // self refresh exit time[tCK]   `define  tREFmax  64000000  // refresh time(64ms)[ns]`endif `ifdef SDR_K   `define  tCK3min       7.5  // system clock cycle time(CL=3)[ns]   `define  tCK3max      1000  // system clock cycle time(CL=3)[ns]   `define  tCK2min       7.5  // system clock cycle time(CL=2)[ns]   `define  tCK2max      1000  // system clock cycle time(CL=2)[ns]   `define  tCHWmin       2.5  // clock high pulse width[ns]   `define  tCLWmin       2.5  // clock low pulse width[ns]   `define  tAC3max       5.4  // access time from clock(CL=3)[ns]   `define  tAC2max       5.4  // access time from clock(CL=2)[ns]   `define  tOHmin        2.7  // data-out hold time[ns]   `define  tDSmin        1.5  // data-input setup time[ns]   `define  tDHmin        0.8  // data-input hold time[ns]   `define  tASmin        1.5  // address setup time[ns]   `define  tAHmin        0.8  // address hold time[ns]   `define  tCKSmin       1.5  // CKE setup time[ns]   `define  tCKHmin       0.8  // CKE hold time[ns]   `define  tCSmin        1.5  // command setup time[ns]   `define  tCHmin        0.8  // command hold time[ns]   `define  tOLZmin         1  // clock to data output in Low-Z time[ns]   `define  tOHZ3min      2.7  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ3max      5.4  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ2min      2.7  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tOHZ2max      5.4  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tRCmin         60  // RAS cycle time @ operation[ns]   `define  tRFCmin        65  // RAS cycle time @ auto refresh[ns]   `define  tRCDmin        15  // RAS to CAS delay[ns]   `define  tRASmin        45  // RAS active time[ns]   `define  tRASmax    100000  // RAS active time[ns]   `define  tRPmin         15  // RAS precharge time[ns]   `define  tRRDmin        15  // RAS to RAS bank active delay[ns]   `define  tCCDmin         1  // CAS to CAS delay[tCK]   `define  tWTLmin         0  // write command to data-in delay[tCK]   `define  tDPLmin         2  // data-in to precharge delay[tCK]   `define  tDALmin         4  // data-in to active command[tCK]   `define  tDQZmin         2  // DQM to data-out Hi-Z[tCK]   `define  tDQMmin         0  // DQM to data-in mask[tCK]   `define  tMRDmin         2  // MRS to new command[tCK]   `define  tPROZ3min       3  // precharge to data output Hi-Z(CL=3)[tCK]   `define  tPROZ2min       2  // precharge to data output Hi-Z(CL=2)[tCK]   `define  tPDEmin         1  // power down exit time[tCK]   `define  tSREmin         1  // self refresh exit time[tCK]   `define  tREFmax  64000000  // refresh time(64ms)[ns]`endif `ifdef SDR_H   `define  tCK3min       7.5  // system clock cycle time(CL=3)[ns]   `define  tCK3max      1000  // system clock cycle time(CL=3)[ns]   `define  tCK2min        10  // system clock cycle time(CL=2)[ns]   `define  tCK2max      1000  // system clock cycle time(CL=2)[ns]   `define  tCHWmin       2.5  // clock high pulse width[ns]   `define  tCLWmin       2.5  // clock low pulse width[ns]   `define  tAC3max       5.4  // access time from clock(CL=3)[ns]   `define  tAC2max         6  // access time from clock(CL=2)[ns]   `define  tOHmin        2.7  // data-out hold time[ns]   `define  tDSmin        1.5  // data-input setup time[ns]   `define  tDHmin        0.8  // data-input hold time[ns]   `define  tASmin        1.5  // address setup time[ns]   `define  tAHmin        0.8  // address hold time[ns]   `define  tCKSmin       1.5  // CKE setup time[ns]   `define  tCKHmin       0.8  // CKE hold time[ns]   `define  tCSmin        1.5  // command setup time[ns]   `define  tCHmin        0.8  // command hold time[ns]   `define  tOLZmin         1  // clock to data output in Low-Z time[ns]   `define  tOHZ3min      2.7  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ3max      5.4  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ2min        3  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tOHZ2max        6  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tRCmin         65  // RAS cycle time @ operation[ns]   `define  tRFCmin        65  // RAS cycle time @ auto refresh[ns]   `define  tRCDmin        20  // RAS to CAS delay[ns]   `define  tRASmin        45  // RAS active time[ns]   `define  tRASmax    100000  // RAS active time[ns]   `define  tRPmin         20  // RAS precharge time[ns]   `define  tRRDmin        15  // RAS to RAS bank active delay[ns]   `define  tCCDmin         1  // CAS to CAS delay[tCK]   `define  tWTLmin         0  // write command to data-in delay[tCK]   `define  tDPLmin         2  // data-in to precharge delay[tCK]   `define  tDALmin         5  // data-in to active command[tCK]   `define  tDQZmin         2  // DQM to data-out Hi-Z[tCK]   `define  tDQMmin         0  // DQM to data-in mask[tCK]   `define  tMRDmin         2  // MRS to new command[tCK]   `define  tPROZ3min       3  // precharge to data output Hi-Z(CL=3)[tCK]   `define  tPROZ2min       2  // precharge to data output Hi-Z(CL=2)[tCK]   `define  tPDEmin         1  // power down exit time[tCK]   `define  tSREmin         1  // self refresh exit time[tCK]   `define  tREFmax  64000000  // refresh time(64ms)[ns]`endif `ifdef SDR_8   `define  tCK3min         8  // system clock cycle time(CL=3)[ns]   `define  tCK3max      1000  // system clock cycle time(CL=3)[ns]   `define  tCK2min        10  // system clock cycle time(CL=2)[ns]   `define  tCK2max      1000  // system clock cycle time(CL=2)[ns]   `define  tCHWmin         3  // clock high pulse width[ns]   `define  tCLWmin         3  // clock low pulse width[ns]   `define  tAC3max         6  // access time from clock(CL=3)[ns]   `define  tAC2max         6  // access time from clock(CL=2)[ns]   `define  tOHmin          3  // data-out hold time[ns]   `define  tDSmin          2  // data-input setup time[ns]   `define  tDHmin          1  // data-input hold time[ns]   `define  tASmin          2  // address setup time[ns]   `define  tAHmin          1  // address hold time[ns]   `define  tCKSmin         2  // CKE setup time[ns]   `define  tCKHmin         1  // CKE hold time[ns]   `define  tCSmin          2  // command setup time[ns]   `define  tCHmin          1  // command hold time[ns]   `define  tOLZmin         1  // clock to data output in Low-Z time[ns]   `define  tOHZ3min        3  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ3max        6  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ2min        3  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tOHZ2max        6  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tRCmin         68  // RAS cycle time @ operation[ns]   `define  tRFCmin        68  // RAS cycle time @ auto refresh[ns]   `define  tRCDmin        20  // RAS to CAS delay[ns]   `define  tRASmin        48  // RAS active time[ns]   `define  tRASmax    100000  // RAS active time[ns]   `define  tRPmin         20  // RAS precharge time[ns]   `define  tRRDmin        16  // RAS to RAS bank active delay[ns]   `define  tCCDmin         1  // CAS to CAS delay[tCK]   `define  tWTLmin         0  // write command to data-in delay[tCK]   `define  tDPLmin         1  // data-in to precharge delay[tCK]   `define  tDALmin         4  // data-in to active command[tCK]   `define  tDQZmin         2  // DQM to data-out Hi-Z[tCK]   `define  tDQMmin         0  // DQM to data-in mask[tCK]   `define  tMRDmin         2  // MRS to new command[tCK]   `define  tPROZ3min       3  // precharge to data output Hi-Z(CL=3)[tCK]   `define  tPROZ2min       2  // precharge to data output Hi-Z(CL=2)[tCK]   `define  tPDEmin         1  // power down exit time[tCK]   `define  tSREmin         1  // self refresh exit time[tCK]   `define  tREFmax  64000000  // refresh time(64ms)[ns]`endif `ifdef SDR_P   `define  tCK3min        10  // system clock cycle time(CL=3)[ns]   `define  tCK3max      1000  // system clock cycle time(CL=3)[ns]   `define  tCK2min        10  // system clock cycle time(CL=2)[ns]   `define  tCK2max      1000  // system clock cycle time(CL=2)[ns]   `define  tCHWmin         3  // clock high pulse width[ns]