`define  tCLWmin         3  // clock low pulse width[ns]   `define  tAC3max         6  // access time from clock(CL=3)[ns]   `define  tAC2max         6  // access time from clock(CL=2)[ns]   `define  tOHmin          3  // data-out hold time[ns]   `define  tDSmin          2  // data-input setup time[ns]   `define  tDHmin          1  // data-input hold time[ns]   `define  tASmin          2  // address setup time[ns]   `define  tAHmin          1  // address hold time[ns]   `define  tCKSmin         2  // CKE setup time[ns]   `define  tCKHmin         1  // CKE hold time[ns]   `define  tCSmin          2  // command setup time[ns]   `define  tCHmin          1  // command hold time[ns]   `define  tOLZmin         1  // clock to data output in Low-Z time[ns]   `define  tOHZ3min        3  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ3max        6  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ2min        3  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tOHZ2max        6  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tRCmin         70  // RAS cycle time @ operation[ns]   `define  tRFCmin        70  // RAS cycle time @ auto refresh[ns]   `define  tRCDmin        20  // RAS to CAS delay[ns]   `define  tRASmin        50  // RAS active time[ns]   `define  tRASmax    100000  // RAS active time[ns]   `define  tRPmin         20  // RAS precharge time[ns]   `define  tRRDmin        20  // RAS to RAS bank active delay[ns]   `define  tCCDmin         1  // CAS to CAS delay[tCK]   `define  tWTLmin         0  // write command to data-in delay[tCK]   `define  tDPLmin         1  // data-in to precharge delay[tCK]   `define  tDALmin         3  // data-in to active command[tCK]   `define  tDQZmin         2  // DQM to data-out Hi-Z[tCK]   `define  tDQMmin         0  // DQM to data-in mask[tCK]   `define  tMRDmin         2  // MRS to new command[tCK]   `define  tPROZ3min       3  // precharge to data output Hi-Z(CL=3)[tCK]   `define  tPROZ2min       2  // precharge to data output Hi-Z(CL=2)[tCK]   `define  tPDEmin         1  // power down exit time[tCK]   `define  tSREmin         1  // self refresh exit time[tCK]   `define  tREFmax  64000000  // refresh time(64ms)[ns]`endif `ifdef SDR_S   `define  tCK3min        10  // system clock cycle time(CL=3)[ns]   `define  tCK3max      1000  // system clock cycle time(CL=3)[ns]   `define  tCK2min        12  // system clock cycle time(CL=2)[ns]   `define  tCK2max      1000  // system clock cycle time(CL=2)[ns]   `define  tCHWmin         3  // clock high pulse width[ns]   `define  tCLWmin         3  // clock low pulse width[ns]   `define  tAC3max         6  // access time from clock(CL=3)[ns]   `define  tAC2max         6  // access time from clock(CL=2)[ns]   `define  tOHmin          3  // data-out hold time[ns]   `define  tDSmin          2  // data-input setup time[ns]   `define  tDHmin          1  // data-input hold time[ns]   `define  tASmin          2  // address setup time[ns]   `define  tAHmin          1  // address hold time[ns]   `define  tCKSmin         2  // CKE setup time[ns]   `define  tCKHmin         1  // CKE hold time[ns]   `define  tCSmin          2  // command setup time[ns]   `define  tCHmin          1  // command hold time[ns]   `define  tOLZmin         1  // clock to data output in Low-Z time[ns]   `define  tOHZ3min        3  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ3max        6  // clock to data output in Hi-Z time(CL=3)[ns]   `define  tOHZ2min        3  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tOHZ2max        6  // clock to data output in Hi-Z time(CL=2)[ns]   `define  tRCmin         70  // RAS cycle time @ operation[ns]   `define  tRFCmin        70  // RAS cycle time @ auto refresh[ns]   `define  tRCDmin        20  // RAS to CAS delay[ns]   `define  tRASmin        50  // RAS active time[ns]   `define  tRASmax    100000  // RAS active time[ns]   `define  tRPmin         20  // RAS precharge time[ns]   `define  tRRDmin        20  // RAS to RAS bank active delay[ns]   `define  tCCDmin         1  // CAS to CAS delay[tCK]   `define  tWTLmin         0  // write command to data-in delay[tCK]   `define  tDPLmin         1  // data-in to precharge delay[tCK]   `define  tDALmin         3  // data-in to active command[tCK]   `define  tDQZmin         2  // DQM to data-out Hi-Z[tCK]   `define  tDQMmin         0  // DQM to data-in mask[tCK]   `define  tMRDmin         2  // MRS to new command[tCK]   `define  tPROZ3min       3  // precharge to data output Hi-Z(CL=3)[tCK]   `define  tPROZ2min       2  // precharge to data output Hi-Z(CL=2)[tCK]   `define  tPDEmin         1  // power down exit time[tCK]   `define  tSREmin         1  // self refresh exit time[tCK]   `define  tREFmax  64000000  // refresh time(64ms)[ns]`endif `ifdef SDR64Mx4   `define  data_bits        4 // number of data bit   `define  addr_bits       12 // number of external address bit   `define  col_bits        10 // number of column address bit   `define  bank_size  4194304 // bank depth : 2^(addr_bits + col_bits)   `define  HiZ           4'bz   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, dqm);   input                  dqm;`endif`ifdef SDR64Mx8   `define  data_bits        8 // number of data bit   `define  addr_bits       12 // number of external address bit   `define  col_bits         9 // number of column address bit   `define  bank_size  2097152 // bank depth : 2^(addr_bits + col_bits)   `define  HiZ           8'bz   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, dqm);   input                  dqm;`endif`ifdef SDR64Mx16   `define  data_bits       16 // number of data bit   `define  addr_bits       12 // number of external address bit   `define  col_bits         8 // number of column address bit   `define  bank_size  1048576 // bank depth : 2^(addr_bits + col_bits)   `define  HiZ          16'bz   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, udqm, ldqm);   input                  udqm;   input                  ldqm;`endif`ifdef SDR128Mx4   `define  data_bits        4 // number of data bit   `define  addr_bits       12 // number of external address bit   `define  col_bits        11 // number of column address bit   `define  bank_size  8388608 // bank depth : 2^(addr_bits + col_bits)   `define  HiZ           4'bz   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, dqm);   input                  dqm;`endif`ifdef SDR128Mx8   `define  data_bits        8 // number of data bit   `define  addr_bits       12 // number of external address bit   `define  col_bits        10 // number of column address bit   `define  bank_size  4194304 // bank depth : 2^(addr_bits + col_bits)   `define  HiZ           8'bz   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, dqm);   input                  dqm;`endif`ifdef SDR128Mx16   `define  data_bits       16 // number of data bit   `define  addr_bits       12 // number of external address bit   `define  col_bits         9 // number of column address bit   `define  bank_size  2097152 // bank depth : 2^(addr_bits + col_bits)   `define  HiZ          16'bz   module SDR(clk, cke, cs_n, ras_n, cas_n, we_n, ba, addr, dq, udqm, ldqm);   input                  udqm;   input                  ldqm;`endifinput                  clk;input                  cke;input                  cs_n;input                  ras_n;input                  cas_n;input                  we_n;input            [1:0] ba;input [`addr_bits-1:0] addr;inout [`data_bits-1:0] dq;`protected;XJB1SQd5DT^<3fKD:lPT@:j>UlQRh=9p<?CJ8=1c5??ACd?V\36qYmGf3DW\cYo:9^X:am>0C]n>2=hqCm95LKq62bVFUBM6eKVF8k6_?q_`CmhO9;Z93A@cElSH02pUm^o6k6YI`cmZceh1P6Qqagi5L2_;1;aPUWG<?b3Fa_ZpC0mI7l8S46V>eG\e6mKkb?O[`fg62[\p?P:E3L^>7C2T`K7;p@eVnZ98coiV9Y4oTp3;CTJ];f@DE7QM5Y\Z>TlK7\3nQOhciE>iI[nDZR9FfqJb?`C5g[NLFjkCmfQY_]h9I``5=^EI8ZEPlf;c3XV1gq\bS[TYbeTIO]kbAFp0ECP?nNO0d2RCTkEiJQLhAHD;9qmWW?Q=G@`IEWZmPkg\021AcPEP3cO_Wq_;e6Ll3Bm6dX]7H<fTXIZ\gF4mO<P5UL;2:;H6PFD>0DLE^Z6kVA;]GUDT^faL_oTVeWLn3lm6dX]7H<fTXIZ7gF6=0Ul6g\PA;hgHaIq@4@I7<BSWXUdhE\44hmeW<54TPKg8234q^Ok9iC_RG4jBA\0mX3F9>M;_XQAa4gfAR`]DA932dKge^]aeYC36USRgfLoVOd@kMAp:8nRa]jF0O\Y5<CJD[cnqfAObHGZU]2;D1dQDqh0J`;^8XmTJWmY:@63l:doJTmanpQWPD_K_k;n45iNSknoYe[X3H6R5AB[:iTScDMlUDLT3hlh_E2iT\Qk:A_N4YpjfPLok_f:@=VG1FggKLX?lBjPUfok0d4Lm]Y3RMWqA8hgIb@^o1TWYVJej`;Z_AqLbb;;6@YW6D8C8M2McSKh]:kEGEIo[MM_T=\8dGC4Udh\@WCmLYPn3G6HTCI\80b>Y]q`A=[G]e=N9J^a;0l<FGfjLffL_1\]3p^3_1LA[<PK;fbdK@[aDVdkcefU\V@0?f7bpL19R>diLqhki4YFWGLj:CnB7UHjd3OfM@@?H8G6:WI@3MXeYXM@qLZ1XQdmNKF9G8J[8=2AnglKD6L]C:iTOeCiKEfk_8d=6WmWLE1GAVmhPK9:VqfN5_Cl]NaHji6@XG2ma=>ZqbI<jk\FaWKiabS_<VF\WSF:HI9I[^2?D5Bjqjf0@TA;?4DUkV_2aXb5Hd4D>pU1V1e8KYAG;ke\aeMDlTXQ0WgmKqbHQ^jI0MRUg^mKCZIcYW:eLCL6Gq058h9`@`V=f5T5dFS<]_4Sg^p=3k_>5?LI=@M05ed]GC\UOOW=kK4aWpf^C\Add9gAbUOEH3d?Zbb^4Fo;83]01gI1D@nG1A=:MTXNZ=ZJCMQKno3KEBZT]o\[ABm`Mq[iGX[cE;PN2FTVaNMX4ENo^lbaMq\>H7DD]clenJhGc^h0@ioe1=DL_p6hDGBJaYH<WV_1?W?`oNidanS:Bq1?Nh[36a@BQc:GHMR:jHn0bR[SHGX^q27HfHoM8RKeU^8<cCQhThbhF8P^qM^X<`gXElEa3:5oiSCFRYOLL1=KiJNF4Jh\Q^i;9KFR9Z^>\P=l;?Q`[5W9@Pb>qobYkiji`4R5^_?cHic:Y0MSLWjo:85pFJ4bZ[b0M061FR\iFTVVWUX?[40SY6qY5i8aD8aQl4clm;B_==h>mnWhcme6Lj9U7HpOoAJd8P5FVBFPXe?@jMRNG8[ZM]12ZT0942p=0@O^;B0nb``oASK_5j`qRNIOZ9Wf4`Va8L2Pk@Q?2<dD2ToOVn?BpZOj\ScL[<40BDdG1?oYV@\FFKKJii?gCco5qo1WeGX`?I]c;hY[N2SX0OD_]]I_210g0[H`ERe[bqXJbfm?QV[[Zg9_TN0e[6NS3:>gIXL000MKmJAT`MpU\<[2S:Ub2ETjeNRBTn[c]:@C_SV[_S83SUSqWC;=b3Bgg>bdJg<?fiQLnd9hOfe_mYY`3GI0IEPM?fEY:<o<OCh\VS7ED;a[Zi2[\8k7hY5NqgA20HeABqC44CZ^^\Bha0QB30@ZXjoJE_VUX4k;77@=@T3hTC_:AQqc3k4W8i`g4;YE:kY[_b@6ACcN]`paLV3LiNeZoD^IldFFMLhA4oloIPgCG^CqWQ02Yc?QNkXAAUG7VP1p4=UiYYhGn>LA:i9QY>V3eOUNpgI;B3BBkhV3CW:cIPYMifIDZ3_[qmK;=:[n69_TfIaeBH1Vq>5lb=9n=VJMM73lT:RU;Kbq3cdaU79?mO?c=cdVf[VAd>pM^72T3fef35L_0nbF=m7CXpISJ4hh3^^eU<hJ`\An3KodYjdeUpHd4V^jKlZb4V6jGj`8iJ3mp?OeC>I9mG]Qc^2a<XDLa2hqZ`W`[`BC^DYS_9Ih>G0>dIp?2[OHCCUhDZOJFL\Ihd>dipOghD@m^@?1;eX\iJiYIqNHMb@;@i2lkVal4X5mPTb2d\BBVI;k2>UKf5d0Mp=<1o]KgHq:\]I86Z<5075NM^C?@EdUc[??V9f5[o5a?D6J9U]<IYN9:dX@1dkLk>@<YAA\0lcVOJ[pnh:N5oC;FkSDmikJ8UO59N:QdZOeAP56>AEUnM`pPj;_D\hgW]99[2iMC0kf_khh6NU<f<Tbo>3VUI?hC?0`qFAkP`LA6AjV6dTNea<1;7B<WpeQHAM>Z4>>cEPMeo:DAY>kS3CS>p_\i9[;kJcR6JcK`2jRKg6`efT^2qU\dd6[d7IJmFRc]9FcV1RUUiWk=p2=9;k5<DXYhk<nbZMK96I0a>i:Y=41oh;baq^FSYW99`]8jeh4:SRkjJWon?I<Ma8nA2>eQp`Q=V]iW5j]3;SEOVdM_nAGjhCLB_eeqoRYSXYX_<B[85i\=fim^KK`3SKeKDcK\<oG>^YZK;D]SJ;0C4PYV\Q`q:lG3i8gf5Q;olo<d[XO7Zgf>S3gC^Wq^fnMDPQ4hD2d_ehPVOSo<T4MbXl`d;_;O^npVOS>]lYM56nka`>oD]I@U8q^`?\in]4Y>WgGYi@?hI=bCJ7eEonT:ObcVGk9GMRAGJWLJDBQ:lIEON5RhFk18=DpffMYU7;Oej2\Ail9lT:S3=p>l4^;ADi8F6JaKMdXDAenaq\mX;oJ7L_ngclKGmG=@2QSq\2oomA0ccE\b857N`hmqXMNGN_gOeRC[Q^:<RBQ^CBm`NR4aF?;Y_V>e_bfDp4mhacf=d8YK<ca4mV\Y<gaaVFhbSYbpAMHL<WE9Z:NXcA]:;8HnENGb@@2pd=cDl?EFX=VFY90haaH]J`obTeBqBXWnL:\i03=5eDhgnRdboeq;29E;KF=R^odMOOoHHPEZPjf:BLChkmS^4:Gp;gKWMLl8:QBSf4h`6=67YGl4hj4Y:U0a?[U:9fYqh2GJ?Mn\YTeZD_C2B5NEN1_IqI7WVO_iFeD=9Gh52?g>H?hP9fBEIaL0D]7M0CicU?ibma3^0T6nD`NPZR1JhpYP2S`S>=RGg6Q49LE?\6DB<qffGFkHN@q]@BP6EKl106C2\7A]k4i3Oee_ede[;iPL1Rk?9_qMdchTES;[^GH:LSco1nb:I1fOO0RM4B?TIYZNY\gCY3pgD^Ik@Oi20=M7a0;2_FD=nGd?_T]YZJk]K\FZ3=5K[bN6Bqb=d3Wm;_IH4i8^E>?Y68]]aIqFOV5D8E;WbXI_E\fW:LD0k3Mfm;q`X_Z@AfP0P9XXKJiG^SgE<C6\1gp<:[EM]9NIJ31L[pSUnmbFgc^dHJXVM61[05m9G2AT3pkNE<m8EJ?@:Z0^LeKCEOcFab^5@^k<kAJFop]eToTFmG9i2>1Gf4MKWG6jMoJN@A>U=[0l6qUlHLZXj7Ln00O^k1fm^Th;VA3VRe34qC8