?? mt48lc8m16a2.vhd
字號:
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC8M16A2.VHD
-- Version: 0.0c
-- Date: April 8th, 1999
-- Model: Behavioral
-- Simulator: Model Technology VLOG (PC version 4.7i)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: sphuynh@micron.com
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC8M16A2 (2Mb x 16 x 4 Banks)
--
-- Description: Micron 64Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.mti_pkg.ALL;
ENTITY mt48lc8m16a2 IS
GENERIC (
tAC : TIME := 5.0 ns; -- Timing parameter for -8E device
tAH : TIME := 1.0 ns;
tAS : TIME := 2.0 ns;
tCH : TIME := 3.0 ns;
tCL : TIME := 3.0 ns;
tCK : TIME := 7.5 ns; -- 133mhz operation
-- tCK : TIME := 10.0 ns; -- 100mhz operation
tDH : TIME := 1.0 ns;
tDS : TIME := 2.0 ns;
tCKH : TIME := 1.0 ns;
tCKS : TIME := 2.0 ns;
tCMH : TIME := 1.0 ns;
tCMS : TIME := 2.0 ns;
tHZ : TIME := 6.0 ns;
tOH : TIME := 3.0 ns;
tMRD : INTEGER := 2;
tRAS : TIME := 50.0 ns;
tRC : TIME := 70.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 20.0 ns;
tWR : INTEGER := 2;
addr_bits : INTEGER := 12;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '0';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '0';
Cas_n : IN STD_LOGIC := '0';
We_n : IN STD_LOGIC := '0';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc8m16a2;
ARCHITECTURE behave OF mt48lc8m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits - 1 DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk, RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
VARIABLE WR_chk : Array4xI := (0 & 0 & 0 & 0);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : BIT_VECTOR (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits - 1) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
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