library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity seven is
    Port ( A : in  STD_LOGIC_VECTOR(0 to 6);
           G : buffer  STD_LOGIC;
           R : out  STD_LOGIC);
end seven;

architecture sevenselection of seven is
signal y: STD_LOGIC_VECTOR(0 to 5);
COMPONENT f_adder
port(ain,bin,cin  : IN STD_LOGIC;
         cout,sum   : OUT STD_LOGIC);
END COMPONENT;
begin
u1: f_adder PORT MAP (A(0),A(1),A(2),y(0),y(1));
u2: f_adder PORT MAP (A(3),A(4),A(5),y(2),y(3));
u3: f_adder PORT MAP (y(1),y(3),A(6),y(4),y(5));

process
variable a:std_logic_vector(2 downto 0); 
begin
a:="000";
IF (y(0)='1')
THEN  a:=a+2;
end if;
IF (y(2)='1')
THEN  a:=a+2;
end if;
IF (y(4)='1')
THEN  a:=a+2;
end if;
IF (y(5)='1')
THEN  a:=a+1;
end if;
G<=a(2);
R<=not(G);
end process; 
end sevenselection;