Release 9.2.04i Map J.40Xilinx Map Application Log File for Design 'eccGen256byte'Design Information------------------Command Line   : d:\Xilinx92i\bin\nt\map.exe -ise
E:/work/store/FPGA/eccGen256byte/eccGen256byte.ise -intstyle ise -p
xc2vp30-ff1152-7 -cm area -pr b -k 4 -c 100 -tx off -o eccGen256byte_map.ncd
eccgen256byte.ngd eccGen256byte.pcf Target Device  : xc2vp30Target Package : ff1152Target Speed   : -7Mapper Version : virtex2p -- $Revision: 1.36 $Mapped Date    : Fri Apr 11 23:49:40 2008Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary--------------Design Summary:Number of errors:      0Number of warnings:    2Logic Utilization:  Number of Slice Flip Flops:          44 out of  27,392    1%  Number of 4 input LUTs:              54 out of  27,392    1%Logic Distribution:  Number of occupied Slices:           36 out of  13,696    1%  Number of Slices containing only related logic:      36 out of      36  100%  Number of Slices containing unrelated logic:          0 out of      36    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs:             61 out of  27,392    1%  Number used as logic:                54  Number used as a route-thru:          7  Number of bonded IOBs:               36 out of     644    5%  Number of PPC405s:                   0 out of       2    0%  Number of GCLKs:                      1 out of      16    6%  Number of GTs:                        0 out of       8    0%  Number of GT10s:                      0 out of       0    0%Total equivalent gate count for design:  718Additional JTAG gate count for IOBs:  1,728Peak Memory Usage:  206 MBTotal REAL time to MAP completion:  6 secs Total CPU time to MAP completion:   3 secs NOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Mapping completed.See MAP report file "eccGen256byte_map.mrp" for details.