library	ieee;
use	ieee.std_logic_1164.all;
use	ieee.std_logic_unsigned.all;

entity	f_div	is
	port(mclkin	:in	std_logic;
			clkout6m	:out	std_logic);
end	entity	f_div;

architecture	f_hav	of	f_div	is
	signal	div_clk1 :std_logic;
    signal  clk1 :std_logic;
	begin
	div:process(mclkin)
        variable	clkcounter1	:integer	range	0 to	100;
		begin
			if mclkin'event	and	mclkin='1'	then
                clkcounter1:=clkcounter1+1;
                if	clkcounter1=48 then
 				  div_clk1<=not div_clk1;
				  clkcounter1:=0;
				end	if;
			end	if;
			clkout6m<=not div_clk1;
		end	process;
end	architecture;