--ddsc1;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity ddsc1 is
  generic(freq_width : integer :=10;
          phase_width : integer :=10;
          adder_width : integer :=10;
          romad_width : integer :=10;
          rom_d_width : integer :=8);
  port(clk1 : in std_logic;
       acc : in std_logic_vector(adder_width-1 downto 0);
       freqin1 : in std_logic_vector(freq_width-1 downto 0);
       phasein1 : in std_logic_vector(phase_width-1 downto 0);
       accout: out std_logic_vector(adder_width-1 downto 0);
       ddsout : out std_logic_vector(romad_width downto 0));

end entity ddsc1;
architecture behave of ddsc1 is
  signal acc1: std_logic_vector(adder_width-1 downto 0);
  signal romaddr: std_logic_vector(romad_width downto 0);
  signal freqw: std_logic_vector(freq_width-1 downto 0);
  signal phasew: std_logic_vector(phase_width-1 downto 0);
begin
  process(clk1)
  begin
    if(clk1'event and clk1='1') then
      freqw<=freqin1;
      phasew<=phasein1;
      acc1<=acc+freqw;
    end if;
  end process;
romaddr<=acc1+phasew;
accout<=acc1;
ddsout<=romaddr;
end architecture behave;