LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
 
ENTITY s_machine IS
PORT(CLK,RESET :IN STD_LOGIC;
   STATE_INPUTS:IN STD_LOGIC_VECTOR(0 TO 1);
   COMB_OUTPUTS:OUT STD_LOGIC_VECTOR(0 TO 5);
              Q:BUFFER INTEGER RANGE 0 TO 31);
END s_machine ;

ARCHITECTURE behv OF s_machine IS
TYPE FSM_ST IS (s0,s1,s2,s3);
SIGNAL CURRENT_STATE,NEXT_STATE:FSM_ST;
BEGIN
REG:PROCESS(RESET,CLK)
BEGIN
IF RESET ='1' THEN CURRENT_STATE<=s3;
ELSIF CLK='1' AND CLK'EVENT THEN 
CURRENT_STATE<=NEXT_STATE;
Q<=Q+1;
END IF;
END PROCESS;
COM:PROCESS(CURRENT_STATE,STATE_INPUTS)
BEGIN 
CASE CURRENT_STATE IS
WHEN s0=>COMB_OUTPUTS<="100001";
IF STATE_INPUTS="00" THEN NEXT_STATE<=s0;
ELSE NEXT_STATE<=s1;
END IF;
WHEN s1=>COMB_OUTPUTS<="010010";
IF STATE_INPUTS="00" THEN NEXT_STATE<=s1;
ELSE NEXT_STATE<=s2;
END IF;
WHEN s2=>COMB_OUTPUTS<="001100";
IF STATE_INPUTS="11" THEN NEXT_STATE<=s0;
ELSE NEXT_STATE<=s3;
END IF;
WHEN s3=>COMB_OUTPUTS<="111111";
IF STATE_INPUTS="11" THEN NEXT_STATE<=s3;
ELSE NEXT_STATE<=s0;
END IF;
END CASE;
END PROCESS;
END behv;