library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity balucaideng is 
port(clk,clr:in std_logic;
     l:out std_logic_vecyor(8 downto 1));
end;


architecture a of balucaideng is 
begin
  process(clk,clr)
  begin
    if clr='0' then l<="1111111";
     else clk'event and clk='1' then
      l<="00000000"
      l<="11110000"
      l<="00001111"
      l<="10101010" 
      l<="01010101"
      l<="00000000"
      l<="11111111"   
end if;
end process