|DAC
CLK => STATUS[4].CLK
CLK => STATUS[3].CLK
CLK => STATUS[2].CLK
CLK => STATUS[1].CLK
CLK => STATUS[0].CLK
CLK => STATUS[5].CLK
RD <= RD1~7.DB_MAX_OUTPUT_PORT_TYPE
WR <= WR1~2.DB_MAX_OUTPUT_PORT_TYPE
CS <= CS1~8.DB_MAX_OUTPUT_PORT_TYPE
ledcs <= ledcs$latch.DB_MAX_OUTPUT_PORT_TYPE
P13 => ~NO_FANOUT~
nRESET => process1~37.IN0
nRESET => process1~53.IN0
nRESET => process1~65.IN0
nRESET => CS1~8.OUTPUTSELECT
nRESET => RD1~7.OUTPUTSELECT
nRESET => WR1~2.OUTPUTSELECT
nRESET => DBUS[7]$latch$r_buf.IN0
nRESET => process1~29.IN0
DBUS[0] <= process1~45
DBUS[1] <= process1~44
DBUS[2] <= process1~43
DBUS[3] <= process1~42
DBUS[4] <= process1~41
DBUS[5] <= process1~40
DBUS[6] <= process1~39
DBUS[7] <= process1~38