{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version " "Info: Version 4.2 Build 178 01/19/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 06 12:46:16 2005 " "Info: Processing started: Wed Apr 06 12:46:16 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off DAC -c ADC " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off DAC -c ADC" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DAC.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DAC.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DAC-DAC " "Info: Found design unit 1: DAC-DAC" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DAC " "Info: Found entity 1: DAC" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "nRESET DAC.vhd(32) " "Warning: VHDL Process Statement warning at DAC.vhd(32): signal \"nRESET\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "DBUS DAC.vhd(76) " "Warning: VHDL Process Statement warning at DAC.vhd(76): signal \"DBUS\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 76 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(87) " "Warning: VHDL Process Statement warning at DAC.vhd(87): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 87 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(89) " "Warning: VHDL Process Statement warning at DAC.vhd(89): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 89 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(91) " "Warning: VHDL Process Statement warning at DAC.vhd(91): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 91 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(93) " "Warning: VHDL Process Statement warning at DAC.vhd(93): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 93 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(95) " "Warning: VHDL Process Statement warning at DAC.vhd(95): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 95 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(97) " "Warning: VHDL Process Statement warning at DAC.vhd(97): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 97 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(99) " "Warning: VHDL Process Statement warning at DAC.vhd(99): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 99 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(101) " "Warning: VHDL Process Statement warning at DAC.vhd(101): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 101 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "AD_VALUE DAC.vhd(103) " "Warning: VHDL Process Statement warning at DAC.vhd(103): signal \"AD_VALUE\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 103 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "CS1 DAC.vhd(123) " "Warning: VHDL Process Statement warning at DAC.vhd(123): signal \"CS1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 123 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "RD1 DAC.vhd(124) " "Warning: VHDL Process Statement warning at DAC.vhd(124): signal \"RD1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 124 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "WR1 DAC.vhd(125) " "Warning: VHDL Process Statement warning at DAC.vhd(125): signal \"WR1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 125 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "DBUS DAC.vhd(30) " "Warning: VHDL Process Statement warning at DAC.vhd(30): signal or variable \"DBUS\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"DBUS\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "AD_VALUE DAC.vhd(30) " "Warning: VHDL Process Statement warning at DAC.vhd(30): signal or variable \"AD_VALUE\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"AD_VALUE\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ledcs DAC.vhd(30) " "Warning: VHDL Process Statement warning at DAC.vhd(30): signal or variable \"ledcs\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ledcs\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 30 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "STATUS\[0\]~12 6 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=6) from the following logic: \"STATUS\[0\]~12\"" {  } { { "DAC.vhd" "STATUS\[0\]~12" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 23 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../altera/quartus42/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus42/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_2b7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_2b7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_2b7 " "Info: Found entity 1: cntr_2b7" {  } { { "db/cntr_2b7.tdf" "" { Text "C:/CVTSOPC/example/DAC/db/cntr_2b7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "P13 " "Warning: No output dependent on input pin \"P13\"" {  } { { "DAC.vhd" "" { Text "C:/CVTSOPC/example/DAC/DAC.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "60 " "Info: Implemented 60 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "45 " "Info: Implemented 45 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 19 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 06 12:46:19 2005 " "Info: Processing ended: Wed Apr 06 12:46:19 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}