|DAC
CLK => STATUS[4].CLK
CLK => STATUS[3].CLK
CLK => STATUS[2].CLK
CLK => STATUS[1].CLK
CLK => STATUS[0].CLK
CLK => STATUS[5].CLK
RD <= RD1~7.DB_MAX_OUTPUT_PORT_TYPE
WR <= WR1~12.DB_MAX_OUTPUT_PORT_TYPE
CS <= CS1~8.DB_MAX_OUTPUT_PORT_TYPE
ledcs <= ledcs$latch.DB_MAX_OUTPUT_PORT_TYPE
P13 <= P131~13.DB_MAX_OUTPUT_PORT_TYPE
RAMCS <= <VCC>
nRESET => process1~47.IN0
nRESET => process1~63.IN0
nRESET => process1~76.IN0
nRESET => CS1~8.OUTPUTSELECT
nRESET => RD1~7.OUTPUTSELECT
nRESET => WR1~12.OUTPUTSELECT
nRESET => P131~13.OUTPUTSELECT
nRESET => process1~22.IN0
nRESET => process1~37.IN0
DBUS[0] <= process1~55
DBUS[1] <= process1~54
DBUS[2] <= process1~53
DBUS[3] <= process1~52
DBUS[4] <= process1~51
DBUS[5] <= process1~50
DBUS[6] <= process1~49
DBUS[7] <= process1~48