Analysis & Synthesis Status : Successful - Sat Dec 06 15:06:59 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : uart_regs
Top-level Entity Name : uart_regs
Family : Stratix
Total logic elements : 392
Total pins : 27
Total virtual pins : 0
Total memory bits : 288
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0