?? uart_regs.pin
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-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.5V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
-- Bank 2: 3.3V
-- Bank 3: 3.3V
-- Bank 4: 3.3V
-- Bank 5: 3.3V
-- Bank 6: 3.3V
-- Bank 7: 3.3V
-- Bank 8: 3.3V
-- Bank 9: 3.3V
-- Bank 10: 3.3V
-- Bank 11: 3.3V
-- Bank 12: 3.3V
-- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
-- It can also be used to report unused dedicated pins. The connection
-- on the board for unused dedicated pins depends on whether this will
-- be used in a future design. One example is device migration. When
-- using device migration, refer to the device pin-tables. If it is a
-- GND pin in the pin table or if it will not be used in a future design
-- for another purpose the it MUST be connected to GND. If it is an unused
-- dedicated pin, then it can be connected to a valid signal on the board
-- (low, high, or toggling) if that signal is required for a different
-- revision of the design.
-- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
-- This pin should be connected to GND. It may also be connected to a
-- valid signal on the board (low, high, or toggling) if that signal
-- is required for a different revision of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
-- RESERVED : Unused I/O pin, which MUST be left unconnected.
-- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
-- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
-- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
-- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
---------------------------------------------------------------------------------
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version
CHIP "uart_regs" ASSIGNED TO AN: EP1S10B672C6
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
GND : A2 : gnd : : : :
RESERVED_INPUT : A3 : : : : 3 :
VCCIO3 : A4 : power : : 3.3V : 3 :
int_o : A5 : output : 3.3-V LVTTL : : 3 : Y
mc_cs3 : A6 : input : 3.3-V LVTTL : : 3 : Y
RESERVED_INPUT : A7 : : : : 3 :
RESERVED_INPUT : A8 : : : : 3 :
RESERVED_INPUT : A9 : : : : 3 :
RESERVED_INPUT : A10 : : : : 3 :
VCCIO3 : A11 : power : : 3.3V : 3 :
RESERVED_INPUT : A12 : : : : 3 :
GND : A13 : gnd : : : :
GND : A14 : gnd : : : :
clk : A15 : input : 3.3-V LVTTL : : 4 : Y
VCCIO4 : A16 : power : : 3.3V : 4 :
srx_pad_i : A17 : input : 3.3-V LVTTL : : 4 : Y
NC : A18 : : : : :
stx_pad_o : A19 : output : 3.3-V LVTTL : : 4 : Y
wb_addr_i[0] : A20 : input : 3.3-V LVTTL : : 4 : Y
wb_addr_i[1] : A21 : input : 3.3-V LVTTL : : 4 : Y
RESERVED_INPUT : A22 : : : : 4 :
VCCIO4 : A23 : power : : 3.3V : 4 :
wb_addr_i[2] : A24 : input : 3.3-V LVTTL : : 4 : Y
GND : A25 : gnd : : : :
wb_dat_i[0] : AA1 : input : 3.3-V LVTTL : : 1 : Y
wb_dat_i[1] : AA2 : input : 3.3-V LVTTL : : 1 : Y
wb_dat_i[2] : AA3 : input : 3.3-V LVTTL : : 1 : Y
wb_dat_i[5] : AA4 : input : 3.3-V LVTTL : : 1 : Y
wb_dat_i[4] : AA5 : input : 3.3-V LVTTL : : 1 : Y
wb_dat_i[6] : AA6 : input : 3.3-V LVTTL : : 1 : Y
RESERVED_INPUT : AA7 : : : : 8 :
wb_dat_i[7] : AA8 : input : 3.3-V LVTTL : : 8 : Y
RESERVED_INPUT : AA9 : : : : 8 :
RESERVED_INPUT : AA10 : : : : 8 :
RESERVED_INPUT : AA11 : : : : 8 :
RESERVED_INPUT : AA12 : : : : 11 :
RESERVED_INPUT : AA13 : : : : 11 :
RESERVED_INPUT : AA14 : : : : 11 :
nIO_PULLUP : AA15 : : : : 7 :
NC : AA16 : : : : :
RESERVED_INPUT : AA17 : : : : 7 :
RESERVED_INPUT : AA18 : : : : 7 :
RESERVED_INPUT : AA19 : : : : 7 :
RESERVED_INPUT : AA20 : : : : 7 :
RESERVED_INPUT : AA21 : : : : 7 :
RESERVED_INPUT : AA22 : : : : 6 :
RESERVED_INPUT : AA23 : : : : 6 :
RESERVED_INPUT : AA24 : : : : 6 :
RESERVED_INPUT : AA25 : : : : 6 :
wb_dat_i[3] : AA26 : input : 3.3-V LVTTL : : 6 : Y
NC : AB1 : : : : :
NC : AB2 : : : : :
RESERVED_INPUT : AB3 : : : : 1 :
RESERVED_INPUT : AB4 : : : : 1 :
RESERVED_INPUT : AB5 : : : : 8 :
NC : AB6 : : : : :
RESERVED_INPUT : AB7 : : : : 8 :
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